CDPCLK4 datasheet(230/274 Pages) ALTERA

230 / 274 page

9–72

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

Design Security

Cyclone III Device Handbook

August 2012

Altera Corporation

Volume 1

AES volatile key zeroization is supported in Cyclone III LS devices. The volatile key

clear and key program JTAG instructions from the device core is supported to protect

Cyclone III LS devices against tampering. You can clear and reprogram the key from

the device core whenever tampering attempt is detected by executing the

KEY_CLR_VREG

and KEY_PROG_VOL JTAG instructions to clear and reprogram the

volatile key, and then reset the Cyclone III LS device by pulling the nCONFIG pin low

for at least 500 ns. When nCONFIG returns to a logic-high level and nSTATUS is released

by the Cyclone III LS device, reconfiguration begins to configure the Cyclone III LS

device with a benign or unencrypted configuration file. After configuration is

successfully completed, observe the cyclecomplete signal from error detection block

to ensure that reconfigured CRAM bits content is correct for at least one error

detection cycle. You can also observe the cyclecomplete and crcerror signals for any

unintentional CRAM bits change.

f cyclecomplete is a signal that is routed from the error detection block to the core for

the purpose of every complete error detection cycle. You must include the

cycloneiiils_crcblock

WYSIWYG atom in your design to use the cyclecomplete

signal. For more information about the SEU mitigation, refer to the SEU Mitigation in

Cyclone III Devices chapter.

VCCBAT is a dedicated power supply for the volatile key storage and not shared with

other on-chip power supplies, such as VCCIO or VCC. VCCBAT continuously supplies

power to the volatile register regardless of the on-chip supply condition. The nominal

voltage for this supply is 3.0 V, while its valid operating range is from 1.2 to 3.3 V. If

you do not use the volatile security key, you may connect the VCCBAT to a 1.8-V, 2.5-V,

or 3.0-V power supply.

1 After power-up, wait for 200 ms (Standard POR) or 9 ms (Fast POR) before beginning

the key programming to ensure that VCCBAT is at its full rail.

1 As an example, BR1220 (-30°C to +80°C) and BR2477A (-40 C to +125°C) are lithium

coin-cell type batteries used for volatile key storage purposes.

f For more information about the battery specifications, refer to the Cyclone III LS Device

Data Sheet chapter.

Cyclone III LS Design Security Solution

Cyclone III LS devices are SRAM-based devices. To provide design security,

Cyclone III LS devices require a 256-bit volatile key for configuration bitstream

encryption.

Design protection

Secure against copying, reverse engineering, and

tampering

Note to Table 9–24:

(1) Key programming is carried out using the JTAG interface.

Table 9–24. Security Key Features

(Part 2 of 2)

Volatile Key Features

Description

CDPCLK4 Scheda tecnica(PDF) 230 Page - Altera Corporation

CDPCLK4 Scheda tecnica(HTML) 230 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL