ADSP-BF705BBCZ-4 datasheet(3/116 Pages) AD

3 / 116 page

Rev. A

Page 3 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

GENERAL DESCRIPTION

The ADSP-BF70x processor is a member of the Blackfin



family of products. The Blackfin processor combines a dual-

MAC 16-bit state-of-the-art signal processing engine, the

advantages of a clean, orthogonal RISC-like microprocessor

instruction set, and single-instruction, multiple-data (SIMD)

multimedia capabilities into a single instruction-set architec-

ture. New enhancements to the Blackfin+ core add 32-bit MAC

and 16-bit complex MAC support, cache enhancements, branch

prediction and other instruction set improvements—all while

maintaining instruction set compatibility to previous Blackfin

products.

The processor offers performance up to 400 MHz, as well as low

static power consumption. Produced with a low-power and low-

voltage design methodology, they provide world-class power

management and performance.

By integrating a rich set of industry-leading system peripherals

and memory (shown in Table 1), the Blackfin processor is the

platform of choice for next-generation applications that require

RISC-like programmability, multimedia support, and leading-

edge signal processing in one integrated package. These applica-

tions span a wide array of markets, from automotive systems to

embedded industrial, instrumentation, video/image analysis,

biometric and power/motor control applications.

Table 1. Processor Comparison

Processor Feature

ADSP-

BF700

ADSP-

BF701

ADSP-

BF702

ADSP-

BF703

ADSP-

BF704

ADSP-

BF705

ADSP-

BF706

ADSP-

BF707

Maximum Speed Grade (MHz)

200

400

Maximum SYSCLK (MHz)

100

200

Package Options

88-Lead

LFCSP

184-Ball

CSP_BGA

88-Lead

LFCSP

184-Ball

CSP_BGA

88-Lead

LFCSP

184-Ball

CSP_BGA

88-Lead

LFCSP

184-Ball

CSP_BGA

GPIOs

L1 Instruction SRAM

48K

L1 Instruction SRAM/Cache

16K

L1 Data SRAM

32K

L1 Data SRAM/Cache

32K

L1 Scratchpad (L1 Data C)

L2 SRAM

128K

256K

512K

1024K

L2 ROM

512K

DDR2/LPDDR (16-bit)

Yes

I2C

Up/Down/Rotary Counter

GP Timer

Watchdog Timer

GP Counter

SPORTs

Quad SPI

Dual SPI

SPI Host Port

USB 2.0 HS OTG

Parallel Peripheral Interface

CAN

UART

Real-Time Clock

Static Memory Controller (SMC)

Yes

Security Crypto Engine

Yes

SD/SDIO (MSI)

4-bit

8-bit

4-bit8-bit

4-Channel 12-Bit ADC

NoYes

YesNoYes

Yes

1 Other speed grades available.

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