ADSP-BF705BBCZ-4 datasheet(13/116 Pages) AD

13 / 116 page

Rev. A

Page 13 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

level specified by the crystal manufacturer. The user should ver-

ify the customized values based on careful investigations on

multiple devices over the required temperature range.

A third-overtone crystal can be used for frequencies above 

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit as

shown in Figure 4. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP (www.ana-

log.com/ee-168).

The same recommendations may be used for the USB crystal

oscillator.

Real-Time Clock

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the processor.

Connect RTC pins RTC_CLKIN and RTC_XTAL with external

components as shown in Figure 5.

The RTC peripheral has dedicated power supply pins so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several pro-

grammable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable

stopwatch countdown, or interrupt at a programmed alarm

time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and a 32,768-day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register. There are two alarms. The first alarm

is for a time of day. The second alarm is for a specific day and

time of that day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch inter-

rupt is enabled and the counter underflows, an interrupt is

generated.

Clock Generation

The clock generation unit (CGU) generates all on-chip clocks

and synchronization signals. Multiplication factors are pro-

grammed to define the PLLCLK frequency. Programmable

values divide the PLLCLK frequency to generate the core clock

(CCLK), the system clocks (SYSCLK, SCLK0, and SCLK1), the

LPDDR or DDR2 clock (DCLK), and the output clock (OCLK).

Writing to the CGU control registers does not affect the behav-

ior of the PLL immediately. Registers are first programmed with

a new value, and the PLL logic executes the changes so that it

transitions smoothly from the current conditions to the new

ones.

SYS_CLKIN oscillations start when power is applied to the

VDD_EXT pins. The rising edge of SYS_HWRST can be

applied after all voltage supplies are within specifications, and

SYS_CLKIN oscillations are stable.

Clock Out/External Clock

The SYS_CLKOUT output pin has programmable options to

output divided-down versions of the on-chip clocks. By default,

the SYS_CLKOUT pin drives a buffered version of the SYS_

CLKIN input. Clock generation faults (for example, PLL

unlock) may trigger a reset by hardware. The clocks shown in

Table 3 can be output on the SYS_CLKOUT pin.

Figure 4. External Crystal Connection

SYS_CLKIN

TO PLL

CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18pF SHOULD BE TREATED AS A MAXIMUM.

18 pF*

BLACKFIN

SYS_XTAL

Figure 5. External Components for RTC

RTC_CLKIN

RTC_XTAL

NOTE: CRYSTAL LOAD CAPACITORS

ARE NOT NECESSARY IN MOST CASES.

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