ADSP-BF705BBCZ-4 datasheet(7/116 Pages) AD

7 / 116 page

Rev. A

Page 7 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

output enable and the input enable of a GPIO pin are both

active, the data signal before the pad driver is looped back to the

receive path for the same GPIO pin.

MEMORY ARCHITECTURE

The processor views memory as a single unified 4G byte address

space, using 32-bit addresses. All resources, including internal

memory, external memory, and I/O control registers, occupy

separate sections of this common address space. The memory

portions of this address space are arranged in a hierarchical

structure to provide a good cost/performance balance of some

very fast, low-latency core-accessible memory as cache or

SRAM, and larger, lower-cost and performance interface-acces-

sible memory systems. See Figure 3.

Internal (Core-Accessible) Memory

The L1 memory system is the highest-performance memory

available to the Blackfin+ processor core.

The core has its own private L1 memory. The modified Harvard

architecture supports two concurrent 32-bit data accesses along

with an instruction fetch at full processor speed which provides

high-bandwidth processor performance. In the core, a 64K byte

block of data memory partners with an 64K byte memory block

for instruction storage. Each data block is multibanked for effi-

cient data exchange through DMA and can be configured as

SRAM. Alternatively, 16K bytes of each block can be configured

in L1 cache mode. The four-way set-associative instruction

cache and the 2 two-way set-associative data caches greatly

accelerate memory access performance, especially when access-

ing external memories.

The L1 memory domain also features a 8K byte data SRAM

block which is ideal for storing local variables and the software

stack. All L1 memory is protected by a multi-parity-bit concept,

regardless of whether the memory is operating in SRAM or

cache mode.

Outside of the L1 domain, L2 and L3 memories are arranged

using a Von Neumann topology. The L2 memory domain is a

unified instruction and data memory and can hold any mixture

of code and data required by the system design. The L2 memory

domain is accessible by the Blackfin+ core through a dedicated

64-bit interface. It operates at SYSCLK frequency.

The processor features up to 1M byte of L2 SRAM, which is

ECC-protected and organized in eight banks. Individual banks

can be made private to any system master. There is also a

512K byte single-bank ROM in the L2 domain. It contains boot

code, security code, and general-purpose ROM space.

OTP Memory

The processor features 4 kB of one-time-programmable (OTP)

memory which is memory-map accessible. This memory stores

a unique chip identification and is used to support secure-boot

and secure operation.

Figure 3. ADSP-BF706/ADSP-BF707 Internal/External Memory Map

PROCESSOR MEMORY MAP

0x 0810 0000 -

Reserved

DDR2 or LPDDR Memory (256 MB)

Reserved

Static Memory Block 1 (8 KB)

Reserved

Static Memory Block 0 (8 KB)

Reserved

SPI2 Memory (128 MB)

Reserved

OTP Memory (4 KB)

Reserved

STM Memory (4 KB)

System MMR Registers (3 MB)

Core MMR Registers (4 MB)

Reserved

L1 Data Block C (8 KB)

L1 Instruction SRAM/Cache (16 KB)

L1 Instruction SRAM (48 KB)

L1 Data Block B SRAM/Cache (16 KB)

L1 Data Block B SRAM (16 KB)

L1 Data Block A SRAM/Cache (16 KB)

L1 Data Block A SRAM (16 KB)

L2 SRAM (1024 KB)

L2 ROM (448 KB)

Boot ROM (64 KB)

0x FFFF FFFF -

0x 9000 0000 -

0x 8000 0000 -

0x 7400 2000 -

0x 7400 0000 -

0x 7000 2000 -

0x 7000 0000 -

0x 4800 0000 -

0x 4000 0000 -

0x 3800 1000 -

0x 3800 0000 -

0x 2030 1000 -

0x 2030 0000 -

0x 2000 0000 -

0x 1FC0 0000 -

0x 11B0 2000 -

0x 11B0 0000 -

0x 11A1 0000 -

0x 11A0 C000 -

0x 11A0 0000 -

0x 1190 8000 -

0x 1190 4000 -

0x 1190 0000 -

0x 1180 8000 -

0x 1180 4000 -

0x 1180 0000 -

0x 0800 0000 -

0x 0408 0000 -

0x 0401 0000 -

0x 0400 0000 -

0x 0000 0000 -

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