ADSP-BF705BBCZ-4 datasheet(8/116 Pages) AD

8 / 116 page

Rev. A

Page 8 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Static Memory Controller (SMC)

The SMC can be programmed to control up to two blocks of

external memories or memory-mapped devices, with very flexi-

ble timing parameters. Each block occupies a 8K byte segment

regardless of the size of the device used.

Dynamic Memory Controller (DMC)

The DMC includes a controller that supports JESD79-2E com-

patible double-data-rate (DDR2) SDRAM and JESD209A low-

power DDR (LPDDR) SDRAM devices. The DMC PHY fea-

tures on-die termination on all data and data strobe pins that

can be used during reads.

I/O Memory Space

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory-mapped registers (MMRs) at addresses in a region of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

Booting

The processor has several mechanisms for automatically loading

internal and external memory after a reset. The boot mode is

defined by the SYS_BMODE input pins dedicated for this pur-

pose. There are two categories of boot modes. In master boot

mode, the processor actively loads data from serial memories. In

slave boot modes, the processor receives data from external host

devices.

The boot modes are shown in Table 2. These modes are imple-

mented by the SYS_BMODE bits of the reset configuration

initiated resets.

SECURITY FEATURES

The ADSP-BF70x processor supports standards-based hard-

ware-accelerated encryption, decryption, authentication, and

true random number generation.

The following hardware-accelerated cryptographic ciphers are

supported:

• AES in ECB, CBC, ICM, and CTR modes with 128-, 192-,

and 256-bit keys

• DES in ECB and CBC mode with 56-bit key

• 3DES in ECB and CBC mode with 3x 56-bit key

The following hardware-accelerated hash functions are

supported:

•SHA-1

• SHA-2 with 224-bit and 256-bit digest

• HMAC transforms for SHA-1 and SHA-2

Public key accelerator is available to offload computation-inten-

sive public key cryptography operations.

Both a hardware-based nondeterministic random number gen-

erator and pseudo-random number generator are available. The

TRNG also provides HW post-processing to meet NIST

requirements of FIPS 140-2, while the PRNG is ANSI X9.31

compliant.

Secure boot is also available with 224-bit elliptic curve digital

signatures ensuring integrity and authenticity of the boot

stream. Optionally, confidentiality is also ensured through AES-

128 encryption.

Secure debug is also employed to allow only trusted users to

access the system with debug tools.

PROCESSOR SAFETY FEATURES

The ADSP-BF70x processor has been designed for functional

safety applications. While the level of safety is mainly domi-

nated by the system concept, the following primitives are

provided by the devices to build a robust safety concept.

Multi-Parity-Bit-Protected L1 Memories

In the processor’s L1 memory space, whether SRAM or cache,

each word is protected by multiple parity bits to detect the single

event upsets that occur in all RAMs. This applies both to L1

instruction and data memory spaces.

ECC-Protected L2 Memories

Error correcting codes (ECC) are used to correct single event

upsets. The L2 memory is protected with a single error correct-

double error detect (SEC-DED) code. By default ECC is

enabled, but it can be disabled on a per-bank basis. Single-bit

errors are transparently corrected. Dual-bit errors can issue a

Table 2. Boot Modes

SYS_BMODE Setting

Boot Mode

No Boot/Idle

SPI2 Master

SPI2 Slave

UART0 Slave

CAUTION

This product includes security features that can be

used to protect embedded nonvolatile memory

contents and prevent execution of unauthorized

code. When security is enabled on this device

(either by the ordering party or the subsequent

receiving parties), the ability of Analog Devices to

conduct failure analysis on returned devices is

limited. Contact Analog Devices for details on the

failure analysis limitations for this device.

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