ADSP-BF705BBCZ-4 datasheet(4/116 Pages) AD

4 / 116 page

Rev. A

Page 4 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

BLACKFIN+ PROCESSOR CORE

As shown in Figure 1, the processor integrates a Blackfin+

processor core. The core, shown in Figure 2, contains two 16-bit

multipliers, one 32-bit multiplier, two 40-bit accumulators

(which may be used together as a 72-bit accumulator), two 

40-bit ALUs, one 72-bit ALU, four video ALUs, and a 40-bit

shifter. The computation units process 8-, 16-, or 32-bit data

from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

operands for compute operations come from the multiported

The core can perform two 16-bit by 16-bit multiply-accumu-

lates or one 32-bit multiply-accumulate in each cycle. Signed

and unsigned formats, rounding, saturation, and complex mul-

tiplies are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, divide primitives, saturation and rounding, and

sign/exponent detection. The set of video instructions include

byte alignment and packing operations, 16-bit and 8-bit adds

with clipping, 8-bit average operations, and 8-bit subtract/abso-

lute value/accumulate (SAA) operations. Also provided are the

compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If a second ALU is used,

quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

Figure 2. Blackfin+ Processor Core

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

DATA ARITHMETIC UNIT

CONTROL

UNIT

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ASTAT

LD0

LD1

DAG0

DAG1

ADDRESS ARITHMETIC UNIT

DA1

DA0

PREG

RAB

BARREL

SHIFTER

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