ADSP-BF705BBCZ-4 datasheet(55/116 Pages) AD

55 / 116 page

Rev. A

Page 55 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

IDD_HIBERNATE

17, 19 Hibernate State Current

VDD_INT = 0 V,

VDD_DMC = 1.8 V,

VDD_EXT = VDD_HADC = VDD_OTP = 

VDD_RTC = VDD_USB = 3.3 V,

TJ = 25°C,

fCLKIN = 0

A

IDD_HIBERNATE

17, 19 Hibernate State Current

Without USB

VDD_INT = 0 V,

VDD_DMC = 1.8 V,

VDD_EXT = VDD_HADC = VDD_OTP = 

VDD_RTC = VDD_USB = 3.3 V,

TJ = 25°C,

fCLKIN = 0,

USB protection disabled



(USB_PHY_CTLDIS = 1)

A

IDD_INT

VDD_INT Current

VDD_INT within operating conditions

table specifications

See IDDINT_TOT

equation on

on Page 56

IDD_RTC

IDD_RTC Current

VDD_RTC = 3.3 V, TJ = 125°C

A

1 Applies to all output and bidirectional signals except DMC0 signals, TWI signals, and USB0 signals.

2 Applies to DMC0_Axx, DMC0_CAS, DMC0_CKE, DMC0_CK, DMC0_CK, DMC0_CS, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS, 

DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, and DMC0_WE signals.

3 Applies to all output and bidirectional signals except DMC0 signals and USB0 signals.

4 Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TDI, and JTG_TMS_SWDIO signals.

5 Applies to DMC0_VREF signal.

6 Applies to JTG_TCK_SWCLK and JTG_TRST signals.

7 Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TCK, and JTG_TRST signals.

8 Applies to JTG_TDI, JTG_TMS_SWDIO, PA_xx, PB_xx, and PC_xx signals when internal GPIO pull-ups are enabled. For information on when internal pull-ups are enabled

for GPIOs. See ADSP-BF70x Designer Quick Reference on Page 38.

9 Applies to USB0_CLKIN signal.

10Applies to PA_xx, PB_xx, PC_xx, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP,

USB0_ID, and USB0_VBC signals.

11 Applies to DMC0_Axx, DMC0_BAxx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_

UDM, DMC0_ODT, DMC0_RAS, and DMC0_WE signals.

12Applies to PA_xx, PB_xx, PC_xx, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS, 

DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, 

DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals.

13Applies to USB0_VBUS signals.

14Applies to all TWI signals.

15Applies to all signals, except DMC0 and TWI signals.

16Applies to all DMC0 signals.

17See the ADSP-BF70x Blackfin+ Processor Hardware Reference for definition of deep sleep and hibernate operating modes.

18Additional information can be found at Total Internal Power Dissipation.

19Applies to VDD_EXT, VDD_DMC, and VDD_USB supply signals only. Clock inputs are tied high or low.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

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