ADSP-BF705BBCZ-4 datasheet(56/116 Pages) AD

56 / 116 page

Rev. A

Page 56 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Total Internal Power Dissipation

Total power dissipation has two components:

1. Static, including leakage current (deep sleep)

2. Dynamic, due to transistor switching characteristics for

each clock domain

Many operating conditions can also affect power dissipation,

including temperature, voltage, operating frequency, and pro-

cessor activity. The following equation describes the internal

current consumption.

IDDINT_TOT = IDDINT_DEEPSLEEP + IDDINT_CCLK_DYN +

IDDINT_PLLCLK_DYN + IDDINT_SYSCLK_DYN + 

IDDINT_SCLK0_DYN + IDDINT_SCLK1_DYN + 

IDDINT_DCLK_DYN + IDDINT_DMA_DR_DYN + 

IDDINT_USBCLK_DYN

IDDINT_DEEPSLEEP is the only item present that is part of the static

power dissipation component. IDDINT_DEEPSLEEP is specified as a

function of voltage (VDD_INT) and temperature (see Table 21).

There are eight different items that contribute to the dynamic

power dissipation. These components fall into three broad cate-

gories: application-dependent currents, clock currents, and data

transmission currents.

Application-Dependent Current

The application-dependent currents include the dynamic cur-

rent in the core clock domain.

Core clock (CCLK) use is subject to an activity scaling factor

(ASF) that represents application code running on the processor

cores and L1/L2 memories (Table 22). The ASF is combined

with the CCLK frequency and VDD_INT dependent data in

Table 23 to calculate this portion.

IDDINT_CCLK_DYN (mA) = Table 23 × ASF

Clock Current

The dynamic clock currents provide the total power dissipated

by all transistors switching in the clock paths. The power dissi-

pated by each clock domain is dependent on voltage (VDD_INT),

operating frequency and a unique scaling factor.

IDDINT_PLLCLK_DYN (mA) = 0.012 × fPLLCLK (MHz) × VDD_INT (V)

IDDINT_SYSCLK_DYN (mA) = 0.120 × fSYSCLK (MHz) × VDD_INT (V)

IDDINT_SCLK0_DYN (mA) = 0.110 × fSCLK0 (MHz) × VDD_INT (V)

IDDINT_SCLK1_DYN (mA) = 0.068 × fSCLK1 (MHz) × VDD_INT (V)

IDDINT_DCLK_DYN (mA) = 0.055 × fDCLK (MHz) × VDD_INT (V)

The dynamic component of the USB clock is a unique case. The

USB clock contributes a near constant current value when used.

Data Transmission Current

The data transmission current represents the power dissipated

when transmitting data. This current is expressed in terms of

data rate. The calculation is performed by adding the data rate

(MB/s) of each DMA-driven access to peripherals, L1, L2, and

external memory. This number is then multiplied by a weighted

data-rate coefficient and VDD_INT:

IDDINT_DMADR_DYN (mA) = Weighted DRC × Total Data Rate

(MB/s) × VDD_INT (V)

A weighted data-rate coefficient is used because different coeffi-

cients exist depending on the source and destination of the

transfer. For details on using this equation and calculating the

weighted DRC, see the related Engineer Zone material. For a

quick maximum calculation, the weighted DRC can be assumed

to be 0.0497, which is the coefficient for L1 to L1 transfers.

Table 20. IDDINT_USBCLK_DYN Current

Is USB Enabled?

IDDINT_USBCLK_DYN (mA)

Yes – High-Speed Mode

13.94

Yes – Full-Speed Mode

10.83

Yes – Suspend Mode

5.2

0.34

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