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ADSP-BF705BBCZ-4 Scheda tecnica(PDF) 1 Page - Analog Devices |
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ADSP-BF705BBCZ-4 Scheda tecnica(HTML) 1 Page - Analog Devices |
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1 / 116 page  Blackfin+ is a trademark of Analog Devices, Inc.; Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin+ Core Embedded Processor ADSP-BF700/701/702/703/704/705/706/707 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Blackfin+ core with up to 400 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin products Low-cost packaging 88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm), RoHS compliant 184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm pitch), RoHS compliant Low system power with < 100 mW core domain power at 400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION PERIPHERALS FEATURES See Figure 1, Processor Block Diagram and Table 1, Processor Comparison MEMORY 136 kB L1 SRAM with multi-parity-bit protection (64 kB instruction, 64 kB data, 8 kB scratchpad) Large on-chip L2 SRAM with ECC protection 256 kB, 512 kB, 1 MB variants On-chip L2 ROM (512 kB) L3 interface (CSP_BGA only) optimized for lowest system power, providing 16-bit interface to DDR2 or LPDDR DRAM devices (up to 200 MHz) Security and one-time-programmable memory Crypto hardware accelerators Fast secure boot for IP protection memDMA encryption/decryption for fast run-time security Figure 1. Processor Block Diagram PERIPHERALS 1× RTC 3× MDMA STREAMS 1× MSI (SD/SDIO) 2× UART STATIC MEMORY CONTROLLER 2× SPORT 1× PPI 8× TIMER 2× CAN 1× COUNTER 1× TWI 1× USB 2.0 HS OTG GPIO SYSTEM CONTROL BLOCKS HARDWARE FUNCTIONS EXTERNAL BUS INTERFACES LPDDR DDR2 SYSTEM FABRIC EMULATOR TEST & CONTROL PLL & POWER MANAGEMENT FAULT MANAGEMENT EVENT CONTROL WATCHDOG 16 MEMORY PROTECTION 136K BYTE PARITY BIT PROTECTED L1 SRAM INSTRUCTION/DATA B ANALOG SUB SYSTEM CRYPTO ENGINE (SECURITY) SYSTEM PROTECTION 512K BYTE ROM UP TO 1M BYTE SRAM ECC-PROTECTED (& DMA MEMORY PROTECTION) L2 MEMORY HADC OTP MEMORY DYNAMIC MEMORY CONTROLLER SPI HOST PORT 2× CRC 2x QUAD SPI 1x DUAL SPI |
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