ADSP-BF705BBCZ-4 datasheet(18/116 Pages) AD

18 / 116 page

Rev. A

Page 18 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

ADSP-BF70x DETAILED SIGNAL DESCRIPTIONS

Table 6 provides a detailed description of each pin.

Table 6. ADSP-BF70x Detailed Signal Descriptions

Port Name

Direction

Description

CAN_RX

Input

Receive. Typically an external CAN transceiver's RX output.

CAN_TX

Output

Transmit. Typically an external CAN transceiver's TX input.

CNT_DG

Input

Count Down and Gate. Depending on the mode of operation this input acts either as a count down

signal or a gate signal Count Down - This input causes the GP counter to decrement Gate - Stops the

GP counter from incrementing or decrementing.

CNT_UD

Input

Count Up and Direction. Depending on the mode of operation this input acts either as a count up

signal or a direction signal Count Up - This input causes the GP counter to increment Direction - Selects

whether the GP counter is incrementing or decrementing.

CNT_ZM

Input

Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the

pressing of a pushbutton.

DMC_Ann

Output

Address n. Address bus.

DMC_BAn

Output

Bank Address Input n. Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE

command is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR,

EMR2, and/or EMR3) are loaded during the LOAD MODE REGISTER command.

DMC_CAS

Output

Column Address Strobe. Defines the operation for external dynamic memory to perform in

conjunction with other DMC command signals. Connect to the CAS input of dynamic memory.

DMC_CK

Output

Clock. Outputs DCLK to external dynamic memory.

DMC_CK

Output

Clock (Complement). Complement of DMC_CK.

DMC_CKE

Output

Clock enable. Active high clock enables. Connects to the dynamic memory's CKE input.

DMC_CSn

Output

Chip Select n. Commands are recognized by the memory only when this signal is asserted.

DMC_DQnn

I/O

Data n. Bidirectional Data bus.

DMC_LDM

Output

Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled

on both edges of the data strobe by the dynamic memory.

DMC_LDQS

I/O

Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with

Read Data. May be single-ended or differential depending on register settings.

DMC_LDQS

I/O

Data Strobe for Lower Byte (complement). Complement of LDQS. Not used in single-ended mode.

DMC_ODT

Output

On-die termination. Enables dynamic memory termination resistances when driven high (assuming

the memory is properly configured). ODT is enabled/disabled regardless of read or write commands.

DMC_RAS

Output

Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction

with other DMC command signals. Connect to the RAS input of dynamic memory.

DMC_UDM

Output

Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled

on both edges of the data strobe by the dynamic memory.

DMC_UDQS

I/O

Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with

Read Data. May be single-ended or differential depending on register settings.

DMC_UDQS

I/O

Data Strobe for Upper Byte (complement). Complement of UDQSb. Not used in single-ended mode.

DMC_VREF

Input

Voltage Reference. Connect to half of the VDD_DMC voltage.

DMC_WE

Output

Write Enable. Defines the operation for external dynamic memory to perform in conjunction with

other DMC command signals. Connect to the WE input of dynamic memory.

PPI_CLK

I/O

Clock. Input in external clock mode, output in internal clock mode.

PPI_Dnn

I/O

Data n. Bidirectional data bus.

PPI_FS1

I/O

Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.

PPI_FS2

I/O

Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.

PPI_FS3

I/O

Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.

HADC_VINn

Input

Analog Input at channel n. Analog voltage inputs for digital conversion.

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