MX66L51235FMI-10G datasheet(64/83 Pages) MCNIX

64 / 83 page

MX66L51235F

Rev. 1.1, August 02, 2016

P/N: PM1832

9-27. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)

instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to

"1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,

SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of

application. The other function descriptions are as same as standard page program.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the "9-10. Enter

4-byte mode (EN4B)" section.

The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte

address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.

If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector

Protect Mode), the Quad Page Program (4PP) instruction will not be executed.

A20

A21 A17

A16 A12 A8 A4 A0

A13 A9 A5 A1

3456789

6 Address cycle

Data

Byte 1

Data

Byte 2

Data

Byte 3

Data

Byte 4

A22 A18 A14 A10 A6 A2

A23 A19 A15 A11 A7 A3

SCLK

CS#

SIO0

SIO1

SIO3

SIO2

38h

Command

10 11 12 13 14 15 16 17 18 19 20 21

Mode 3

Mode 0

Figure 57. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

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