MX66L51235FMI-10G datasheet(58/83 Pages) MCNIX

58 / 83 page

MX66L51235F

Rev. 1.1, August 02, 2016

P/N: PM1832

Figure 47. Sector Erase (SE) Sequence (SPI Mode)

345678 9

29 30 31

A23 A22

A2 A1 A0

MSB

SCLK

CS#

20h

Command

Mode 3

Mode 0

24-Bit Address

(Note)

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 48. Sector Erase (SE) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

20h

A5 A4

MSB

A3 A2

A1 A0

Command

Mode 3

Mode 0

24-Bit Address

(Note)

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

9-22. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used

for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit

before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 4. Memory Organization")

is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least

significant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to define EAR bit. Address bits [Am-A12] (Am is the most significant address) select

the sector address.

To enter the 4-byte address mode, please refer to the "9-10. Enter 4-byte mode (EN4B)" section.

The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte or 4-byte address

on SI→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE

timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode), the Sector Erase (SE) instruction will not be executed on the block.

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