MX66L51235FMI-10G datasheet(72/83 Pages) MCNIX

Il numero della parte	MX66L51235FMI-10G

Spiegazioni elettronici	3V, 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY

PDF	83 Pages

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Produttore elettronici	MCNIX [Macronix International]

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MX66L51235F

Rev. 1.1, August 02, 2016

P/N: PM1832

9-34-2. SPB Lock Bit (SPBLB)

The Solid Protection Bit Lock Bit (SPBLB) is assigned to control all SPB status. It is unique and volatile.

The default status of this register is determined by Lock Register bit 1 and bit 2 status. Refer to SPB Lock Register

for more SPB Lock information.

When under Solid Protect Mode, there is no software command sequence requested to unlock this bit. To clear the

SPB lock bit, just take the device through a reset or a power-up cycle. When under Password Protection Mode, in

order to prevent modification, the SPB Lock Bit must be set after all SPBs are setting the desired status.

SPB Lock Register

Bit

Description

Bit Status

Default

Type

7-1

Reserved

0000000

Volatile

SPBLK (Lock SPB Bit)

0= SPB bit protected

1= SPB bit unprotected

Solid protected Mode=1

Password Protected Mode=0

Volatile

Figure 64. SPB Lock Bit Set (SPBLK) Sequence

34567

High-Z

A6h

Command

SCLK

CS#

Mode 3

Mode 0

Figure 65. Read SPB Lock Register (RDSPBLK) Sequence

345678 9 10 11 12 13 14 15

command

7 6543210

High-Z

MSB

7 6543210

MSB

SCLK

CS#

A7h

Mode 3

Mode 0

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