MX66L51235FMI-10G datasheet(9/83 Pages) MCNIX

9 / 83 page

MX66L51235F

Rev. 1.1, August 02, 2016

P/N: PM1832

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after specific command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic

Signature command (RES), and softreset command.

• Advanced Security Features: there are some protection and security features which protect content from

inadvertent write and hostile access.

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be

protected as read only. The protected area definition is shown as Table 2 Protected Area Sizes, the protected

areas are more flexible which may protect various area by setting value of BP0-BP3 bits.

- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status

- In four I/O and QPI mode, the feature of HPM will be disabled.

MX66L51235FMI-10G Scheda tecnica(PDF) 9 Page - Macronix International