MX66L51235FMI-10G datasheet(59/83 Pages) MCNIX

59 / 83 page

MX66L51235F

Rev. 1.1, August 02, 2016

P/N: PM1832

9-23. Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch

(WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "Table 4. Memory

Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte

boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not

executed.

Address bits [Am-A15] (Am is the most significant address) select the 32KB block address. The default read mode is

3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or

to define EAR bit. To enter the 4-byte address mode, please refer to the "9-10. Enter 4-byte mode (EN4B)" section.

The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte or 4-byte

address on SI→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the

tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector

Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block.

Figure 49. Block Erase 32KB (BE32K) Sequence (SPI Mode)

345678 9

29 30 31

A23 A22

MSB

SCLK

CS#

52h

Command

Mode 3

Mode 0

24-Bit Address

(Note)

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 50. Block Erase 32KB (BE32K) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

52h

A5 A4

MSB

A3 A2

A1 A0

Command

Mode 3

Mode 0

24-Bit Address

(Note)

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

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