MX66L51235FMI-10G datasheet(51/83 Pages) MCNIX

51 / 83 page

MX66L51235F

Rev. 1.1, August 02, 2016

P/N: PM1832

Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The SPI and QPI mode

4READ and 4READ4B read commands support the wrap around feature after Burst Read is enabled. To change

the wrap depth, resend the Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the

Burst Read instruction with Wrap Code 1xh. “EBh” supports wrap around feature after wrap around is enabled. Both

SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this instruction. The SIO[3:1] are don't care

during SPI mode.

Data

Wrap Around

Wrap Depth

00h

Yes

8-byte

01h

Yes

16-byte

02h

Yes

32-byte

03h

Yes

64-byte

1xh

CS#

SCLK

SIO

C0h

Mode 3

Mode 0

Figure 38. Burst Read - SPI Mode

Figure 39. Burst Read - QPI Mode

CS#

SCLK

SIO[3:0]

MSB LSB

C0h

Mode 3

Mode 0

Note: MSB=Most Significant Bit

LSB=Least Significant Bit

9-19. Burst Read

The Burst Read feature allows applications to fill a cache line with a fixed length of data without using multiple read

commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting the Burst

Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes) containing the

initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the 8-byte-page-aligned

boundary containing the initial read address.

To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE

→drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.

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