ADIN1300CCPZ-R7 datasheet(32/79 Pages) AD

32 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 32 of 79

CABLE DIAGNOSTICS

The ADIN1300 has on-chip cable diagnostics capabilities. This

cable analysis can be used to detect cable impairments that may

be preventing the establishment of a gigabit link or degrading

performance and can be performed both when the link is up or

when the link is down.

Each time a 100BASE-TX or 1000BASE-T link is brought up,

the ADIN1300 reports an estimate of the cable length based on

the signal processing. This can be read in the cable diagnostics

cable length estimate register (CDIAG_CBL_LEN_EST register,

Address 0xBA25). This estimate is not available for a 10BASE-Te

link. A polarity inversion on each pair is reported in the pair

polarity inversion register bits (PHY_2_STATUS register,

Address 0x001F, Bits[13:10]) and the B_10_POL_INV bit

(PHY_STATUS_1 register, Address 0x001A). Pair swaps are

reported in the pair swap register bits (PAIR_23_SWAP bit,

Address 0x001F and PAIR_01_SWAP bit, Address 0x001A).

When the link is up, the signal quality on each pair is indicated

in the mean square error register for each pair (MSE_A,

MSE_B, MSE_C, and MSE_D registers, Address 0x8402 to

Address 0x8405, Bits[7:0]).

When the link is down, the ADIN1300 can run cable fault

detection using time domain reflectometry (TDR). By transmitting

pulses and analyzing the reflections, the PHY can detect cable

faults like opens, shorts, cross pair shorts, and the distance to

the nearest fault. The PHY can also determine that the pair is

well terminated and does not have any faults. Put the remote

PHY in a power-down state or disconnect the PHY to run cable

fault detection because remote PHY link pulses can interfere

with the analysis of the reflected pulses and can return a pair

busy result.

The cable fault detection is automatically run on all four pairs

looking at all combinations of pair faults by first putting the

PHY in standby (clear the LINK_EN bit, PHY_CTRL_3 register,

Address 0x0017) and then enabling the diagnostic clock (set the

DIAG_CLK_EN bit, PHY_CTRL_1 register, Address 0x0012).

Cable diagnostics can then be run (set the CDIAG_RUN bit in

the CDIAG_RUN register, Address 0xBA1B). The results are

reported for each pair in the cable diagnostics results registers,

CDIAG_DTLD_RSLTS_0, CDIAG_DTLD_RSLTS_1,

CDIAG_DTLD_RSLTS_2, and CDIAG_DTLD_RSLTS_3,

Address 0xBA1D to Address 0xBA20). The distance to the first

fault for each pair is reported in the cable fault distance

registers, CDIAG_FLT_DIST_0, CDIAG_FLT_DIST_1,

CDIAG_FLT_DIST_2, and CDIAG_FLT_DIST_3,

Address 0xBA21 to Address 0xBA24).

ENHANCED LINK DETECTION

The ADIN1300 supports enhanced link detection, which is early

detection and indication of link loss. This is a feature where the

received signal is monitored, and if a significant number of con-

secutive samples of the signal are not as expected, early indication

of link down is indicated. The ADIN1300 can simultaneously

monitor for a significant number of consecutive 0s, a significant

number of consecutive 1s, or a significant number of

consecutive invalid levels.

If enhanced link detection is enabled, the ADIN1300 typically

reacts to a break in the cable within 10 μs and indicates link

down via the LINK_ST pin. If enhanced link detection is not

enabled, the ADIN1300 follows the IEEE standard, and in

100BASE-TX, it can take more than either 350 ms or 750 ms in

1000BASE-T, depending if the PHY is 1000BASE-T master or

1000BASE-T slave.

Enhanced link detection is enabled for 100BASE-TX via the

enhanced link detection 100BASE-TX enable register bits

(FLD_EN register, Address 0x8E27, Bit 5, Bit 3, and Bit 1) and

for 1000BASE-T via the 1000BASE-T enhanced link detection

enable register bits (FLD_EN register, Address 0x8E27, Bit 6,

Bit 4, Bit 2, and Bit 0).

Do not enable 1000BASE-T retrain (clear the

B_1000_RTRN_EN bit, Address 0xA001) if enhanced link

detection is enabled for 1000BASE-T.

The latched status of the enhanced link detection function can

be read via the enhanced link detection status bit, FAST_

LINK_DOWN_LAT (Address 0x8E38).

START OF PACKET INDICATION

The ADIN1300 includes the detection and indication of the

start of packets (SOP) on the transmit and receive side to

support IEEE 1588 time stamp controls and give the MAC more

accurate timing information.

The transmit and receive SOP indication can be made available

at any of the following pins under software configuration:

GP_CLK, LINK_ST, INT_N, and LED_0 using the following

override control registers:



GE_IO_GP_CLK_OR_CNTRL bits, Address 0xFF3C



GE_IO_GP_OUT_OR_CNTRL bits, Address 0xFF3D



GE_IO_INT_N_OR_CNTRL bits, Address 0xFF3E



GE_IO_LED_A_OR_CNTRL bits, Address 0xFF40

The detection of the transmit SOP is done after internal PHY

FIFO so there is a fixed delay between the SOP indication at the

pin to the actual SOP at the MDI pins.

Start of packet indication is enabled via the SOP transmit and

receive enables, (set the SOP_TX_EN bit, and the SOP_RX_EN bit,

Address 0x9428).

The SOP is asserted by default on the first byte or nibble of the

frame. The SOP can be configured to be asserted when the start

frame delimitator (SFD) is detected in the frame. This is

configured by setting the SOP SFD enable bit (SOP_SFD_EN,

Address 0x9428).

The SOP indication, by default, is asserted for the duration of

the frame. The SOP can be configured to be asserted for a

programmable number of cycles. This is configured by setting

the SOP N-cycle enable bit (SOP_NCYC_EN, Address 0x9428),

and the number of cycles in this case is configured via the SOP

ADIN1300CCPZ-R7 Scheda tecnica(PDF) 32 Page - Analog Devices

ADIN1300CCPZ-R7 Scheda tecnica(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Scheda tecnica Scarica

Link URL