ADIN1300CCPZ-R7 datasheet(65/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 65 of 79

Frame Generator Number of Frames Low Register

Address: 0x941D, Reset: 0x0100, Name: FG_NFRM_L

This register is Bits[15:0] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled

or restarted.

Table 91. Bit Descriptions for FG_NFRM_L

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_L

Bits[15:0] of the Number of Frames to be Generated.

0x100

R/W

Frame Generator Done Register

Address: 0x941E, Reset: 0x0000, Name: FG_DONE

This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the

FG_NFRM_H register and FG_NFRM_L register (Address 0x941C and Address 0x941D, respectively).

Table 92. Bit Descriptions for FG_DONE

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_DONE

This bit reads as 1'b1 to indicate that the generation of frames has completed. When set, this bit

goes high and it latches high until it is unlatched by reading.

0x0

FIFO_SYNC Register

Address: 0x9427, Reset: 0x0000, Name: FIFO_SYNC

When set, the transmit FIFO is configured for synchronous operation (except in 1000BASE-T slave mode) to minimize latency.

Table 93. Bit Descriptions for FIFO_SYNC

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FIFO_SYNC

FIFO_SYNC. When set, the transmit FIFO is configured for synchronous operation (except in

1000BASE-T slave mode) to minimize latency.

0x0

R/W

Start of Packet Control Register

Address: 0x9428, Reset: 0x0034, Name: SOP_CTRL

This register controls the start of packet (SOP) detection for IEEE 1588 time stamp controls.

Table 94. Bit Descriptions for SOP_CTRL

Bits

Bit Name

Description

Reset

Access

[15:7]

RESERVED

Reserved.

0x0

[6:4]

SOP_N_8_CYCM_1

When the SOP_NCYC_EN bit is set, the SOP_N_8_CYCM_1 bit field specifies the number

of cycles of the MII RX_CLK clock that the transmit and receive SOP indications remain

asserted. Add 1 to the value specified and then multiply by 8 to get the number of cycles.

Note that the SOP indications are always deasserted at the end of the frame.

0x3

R/W

SOP_NCYC_EN

When this bit is set, the duration of the transmit and receive SOP indications are defined

by the SOP_N_8_CYCM_1 bit field. Otherwise, the SOP indications are set for the duration

of the frame.

0x0

R/W

SOP_SFD_EN

When this bit is set, SFD detection is enabled, so that the SOP signals are asserted when the

SFD in the frame is detected. If this register bit is cleared, the SOP signals are asserted on

the first byte or nibble of the frame. Note that if this signal is changed while packets are

being transmitted or received, the SOP signals may be wrongly asserted. Therefore, only

change the signal while the link is down or when SOP_TX_EN and SOP_RX_EN are cleared.

0x1

R/W

SOP_RX_EN

When set, this bit enables the generation of SOP detection for received frames.

0x0

R/W

SOP_TX_EN

When set, this bit enables the generation of SOP detection for transmitted frames. To

minimize the SOP indication variation, the detection is done after the transmit FIFO for

modes in which the transmit FIFO is used.

0x0

R/W

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