ADIN1300CCPZ-R7 datasheet(5/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 5 of 79

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUTS/OUTPUTS

Applies to MAC interface, MDC pin, MDIO pin, and

INT_N pin

VDDIO = 3.3 V

Input Low Voltage (VIL)

0.8

Input High Voltage (VIH)

2.0

Output Low Voltage (VOL)

0.4

Output low current (IOL) (min) = 4 mA

Output High Voltage (VOH)

2.4

Output high current (IOH) (min) = 4 mA

VDDIO = 2.5 V

VIL

0.7

VIH

1.7

VOL

0.4

IOL (min) = 4 mA

VOH

2.0

IOH (min) = 2 mA

1.7

IOH (min) = 4 mA

VDDIO = 1.8 V

VIL

0.35 ×

VDDIO

VIH

0.65 ×

VDDIO

VOL

0.45

IOL (min) = 2 mA

VOH

VDDIO −

0.45

IOH (min) = 2 mA

AVDD_3P3

Applies to COL/TX_ER function of the

LED_0/COL/TX_ER/PHY_CFG0 pin

VIL

0.8

VIH

2.0

VOL

0.4

IOL (min) = 4 mA

VOH

2.4

IOH (min) = 4 mA

Input Leakage Current High (IIH) and Input

Leakage Current Low (IIL)

μA

Except pins with internal pull-down resistors

LED OUTPUT

Applies to LED_0

Output Drive Current

AVDD_3P3 = 3.3 V

CLOCKS

External Crystal (XTAL)

Requirements for external crystal used on XTAL_I pin

and XTAL_O pin

Crystal Frequency

MHz

Crystal Frequency Tolerance

−50

+50

ppm

Crystal Output Drive Level

<200

µW

Crystal ESR

100

Crystal Load Capacitance (CL)6

XTAL_I Jitter

Over frequency range 10 kHz to 5 MHz

Clock Input Frequency (CLK_IN)

MHz

Requirements for external clock applied to

XTAL_I pin, MII, RGMII modes

MHz

RMII mode

Clock Input Voltage Range (CLK_IN)

2.5

MAC interface capacitive load of 5 pF, REFCLK is disabled.

The DPTH_MII_BYTE register defines whether the programmed transmit first in, first out (FIFO) depth is bytes or nibbles for MII modes (10BASE-Te and 100BASE-TX).

The register defaults to 1, which corresponds to bytes. In MII mode, because the interface is nibble based, the internal prefill in the transmit FIFO is larger and is

observed as longer latency times. The latency specifications in Table 1 have this bit set to 0 for MII.

This 100BASE-TX RGMII transmit latency is where the transit FIFO is programmed for synchronous operation (MAC transmit clock must be synchronous with the

ADIN1300 reference clock), see the FIFO_SYNC register.

This 100BASE-TX RGMII transmit latency is where the MAC transmit clock does not have to be synchronous with the ADIN1300 reference clock and the transmit FIFO

takes care of any phase difference.

The RMII transmit latency depends on the phase relationship between the 50 MHz reference clock and the internal 25 MHz clock. The transmit latency is fixed for a given link.

Where load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics.

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