ADIN1300CCPZ-R7 datasheet(16/79 Pages) AD

16 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 16 of 79

THEORY OF OPERATION

OVERVIEW

The ADIN1300 is a low power, single port, Gigabit Ethernet

transceiver with low latency specifications primarily designed

for industrial Ethernet applications. This design integrates an

EEE PHY core and all associated common analog circuitry, input

and output clock buffering, management interface and

subsystem registers, and MAC interface and control logic to

manage the reset and clock control and hardware pin

configuration.

The ADIN1300 interfaces directly to twisted pair media through

an external transformer and is capable of supporting cable

lengths up to 150 meters at Gigabit speeds and 180 meters when

operating at 100 Mbps or 10 Mbps speeds.

When the 10 Mbps speed is selected, the device operates by

default in 10BASE-Te mode using the 10BASE-Te transmit

levels. The ADIN1300 can be configured via software (using the

B10eEn bit, see Table 100) to operate 10BASE-T mode using the

larger 10BASE-T transmit levels. The only difference between

10BASE-Te and 10BASE-T is the transmit level. A PHY

configured as 10BASE-Te interoperates with a 10BASE-T PHY,

assuming a normal Cat-5 cable is used.

The ADIN1300 provides a suite of diagnostic features enabling

the user to analyze the quality of the link during operation or

while the link is down.

Figure 19 shows a simplified overview of the main channel

blocks. The following sections describe each block.

ANALOG FRONT END (AFE)

The AFE stage consists of a hybrid stage, a programmable gain

amplifier (PGA), and an analog-to-digital convertor (ADC). The

function of the hybrid stage is to remove the transmitted signal

from the input signal, thereby allowing full-duplex operation on

the twisted pair. The PGA stage scales the incoming signal

before it reaches the ADC. The gain stage is controlled and

adjusted based on the output of the ADC to ensure the signal

applied to the ADC is maximized but within range of the ADC.

Physical Media Attachment (PMA)

The PMA block consists of the feed forward equalizer (FFE)

stage, which removes intersymbol interference (ISI).

The twisted pairs of Ethernet cables are not internally shielded

from each other, so signals transmitted on one pair couple across

to the other pairs. When a transmitter does not match to the

line due to mismatches or cable connectors, reflections are

observed as an echo. The echo and crosstalk estimates are

subtracted from the equalizer output.

Baseline wander is an artifact of the external transformer that

attenuates at low frequencies. When there are many symbols with

the same sign transmitted consecutively, the signal at the receiver

reduces. The baseline wander block monitors and corrects to

ensure the likelihood of receiving a symbol error is reduced.

Transmit Functions

1000BASE-T Mode

In 1000BASE-T, the PHY core encodes 8-bit data for transmission

by the PMA as a 4D five-level pulse amplitude modulation

(PAM) signal over the four pairs of cable.

100BASE-TX Mode

For the 100BASE-TX mode, the 4-bit data is first encoded into a

5-bit serial bit stream running at 125 Mbps. This is then sent to

the scrambler where it is encoded to a three-level multilevel

transmit (MLT3) format for transmission by the PMA.

10BASE-Te Mode

For the 10BASE-Te mode, the PHY transmits and receives

Manchester-encoded data.

Receive Functions

1000BASE-T Mode

The PMA decodes the incoming 4D PAM signals into 8-bit

data. After performing compensation and after additional

cleanup, the PMA outputs the data to the receive pins of the

MAC interface.

100BASE-TX Mode

The PMA decodes the incoming 3-level MLT3 sequence into

4-bit data after descrambling and 5-bit to 4-bit decoding.

10BASE-Te Mode

The core decodes the Manchester-encoded received signal.

HYBRID

MDI_0_P

MDI_0_N

MDI_1_P

MDI_1_N

MDI_2_P

MDI_2_N

MDI_3_P

MDI_3_N

RX PATH

TX PATH

MAC

INTERFACE

PCS

PMA

AFE

SUBSYSTEM

ADC

FRAME

GENERATOR

AND CHECKER

FFE

PGA

ECHO

CANCELLER

TRANSMIT

SHAPING

BLW

CORRECTION

CANCELLER

TRELLIS

DECODER

DAC

ENCODE

Figure 19. Simplified Channel Block Diagram

ADIN1300CCPZ-R7 Scheda tecnica(PDF) 16 Page - Analog Devices

ADIN1300CCPZ-R7 Scheda tecnica(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Scheda tecnica Scarica

Link URL