ADIN1300CCPZ-R7 datasheet(19/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 19 of 79

The interface is compatible with both IEEE Standard 802.3

Clause 22 and Clause 45 management frame structures, as

shown in Table 15 and Table 16, respectively, and defined as the

following:

•

Preamble: establishes synchronization at beginning of frame.

•

Start of frame:

•

01 indicates start of Clause 22 frame.

•

00 indicates start of Clause 45 frame.

•

OP: the operation code indicates type of frame transaction.

•

PHYAD/PRTAD: PHY address. MSB first, only the PHY

with matching PHY address hardware configuration

responds.

•

REG ADDR/DEVAD: register address, MSB first.

•

TA: used to avoid contention during a read transition, 2-bit

time spacing between register address field and data field.

•

DATA: 16-bit field, MSB first.

•

ADDRESS/DATA: 16-bit field, MSB first.

•

IDLE: high-Z state, the MDIO line is pulled high by the

pull-up resistor.

The PHY core registers at Address 0x00 to Address 0x01F can

be accessed using the interface specified under Clause 22. The

PHY core extended management interface (EMI) registers and

subsystem registers can be accessed at Address 0x1E using the

interface specified under Clause 45. However, for systems that

do not support this interface, the registers at Address 0x1E can

be accessed via Register 0x0010 and Register 0x0011 using

Clause 22 access.

Interrupt (INT_N)

The ADIN1300 is capable of generating an interrupt to a host

processor or MAC using the INT_N pin in response to a variety of

user-selectable conditions (IRQ_MASK register, Address 0x0018).

The following conditions can be selected to generate an interrupt:

•

Speed change

•

Link status change

•

Receive status change

•

MAC interface FIFO overflow/underflow

•

Idle error counter saturated

•

Autonegotiation page received

•

Autonegotiation status change

•

MDIO synchronization lost

•

Cable diagnostic change

When an interrupt occurs, the system can poll the status of the

interrupt status register (IRQ_STATUS register, Address 0x0019)

on each device to determine the origin of the interrupt.

Table 15. Clause 22 Management Interface Frame Format

Operation

Preamble

Start of Frame

PHYAD[4:0]

REG ADDR[4:0]

DATA[15:0]

IDLE

Read

32 1s

AAAAA

RRRRR

d….d

Write

32 1s

AAAAA

RRRRR

d….d

Table 16. Clause 45 Management Interface Frame Format

Operation

Preamble

Start of Frame

PRTAD[4:0]

DEVAD[4:0]

ADDRESS/DATA[15:0]

IDLE

Address

32 1s

PPPPP

EEEEE

A…...A

Write

32 1s

PPPPP

EEEEE

d….d

Read

32 1s

PPPPP

EEEEE

d….d

Post read Increment Address

32 1s

PPPPP

EEEEE

d….d

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