ADIN1300CCPZ-R7 datasheet(52/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 52 of 79

Bits

Bit Name

Description

Reset

Access

HW_IRQ_EN

When set, this enables the hardware interrupt pin, INT_N, and INT_N is asserted

when an interrupt is generated.

0x0

R/W

1: enable the hardware interrupt pin, INT_N.

0: disable the hardware interrupt pin, INT_N.

Interrupt Status Register

Address: 0x0019, Reset: 0x0000, Name: IRQ_STATUS

The interrupt status register is used to check which interrupts have triggered since the last time it was read. Each bit goes high when the

associated interrupt triggers and then latches high until it is unlatched by reading (note that reading any of the bits in this register unlatches

all of the bits in the register). The bits of IRQ_STATUS go high even when the associated interrupts are not enabled. However, only bits

associated with enabled interrupts are considered when generating the IRQ_PENDING indication.

Table 52. Bit Descriptions for IRQ_STATUS

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x0

CBL_DIAG_IRQ_STAT

If the cable diagnostics interrupt status bit is 1, this indicates that the

associated interrupt triggered since last read. Note that when this bit goes

high, it latches high until it is unlatched by reading.

0x0

MDIO_SYNC_IRQ_STAT

If the MDIO synchronization lost interrupt status bit is 1, this indicates that the

associated interrupt triggered since last read. Note that when this bit goes high,

it latches high until it is unlatched by reading.

0x0

AN_STAT_CHNG_IRQ_STAT

If the autonegotiation status changed interrupt status bit is 1, this indicates

that the associated interrupt triggered since last read. Note that when this bit

goes high, it latches high until it is unlatched by reading.

0x0

RESERVED

Reserved.

0x0

PAGE_RX_IRQ_STAT

If the autonegotiation page received interrupt status bit is 1, this indicates that

the associated interrupt triggered since last read. Note that when this bit goes

high, it latches high until it is unlatched by reading.

0x0

IDLE_ERR_CNT_IRQ_STAT

If the idle error counter saturated interrupt status bit is 1, this indicates that the

associated interrupt triggered since last read. Note that when this bit goes

high, it latches high until it is unlatched by reading.

0x0

FIFO_OU_IRQ_STAT

If the MAC interface RGMII transmit FIFO overflow/underflow interrupt status

bit is 1, this indicates that the associated interrupt triggered since last read.

Note that when this bit goes high, it latches high until it is unlatched by reading.

0x0

RX_STAT_CHNG_IRQ_STAT

If the receive status changed interrupt status bit is 1, this indicates that the

associated interrupt triggered since last read. Note that when this bit goes

high, it latches high until it is unlatched by reading.

0x0

LNK_STAT_CHNG_IRQ_STAT

If the link status changed interrupt status bit is 1, this indicates that the

associated interrupt triggered since last read. Note that when this bit goes

high, it latches high until it is unlatched by reading.

0x0

SPEED_CHNG_IRQ_STAT

If the speed changed interrupt status bit is 1, this indicates that the associated

interrupt triggered since last read. Note that when this bit goes high, it latches

high until it is unlatched by reading.

0x0

IRQ_PENDING

If the interrupt pending status bit is 1, this indicates that an interrupt has

occurred and is pending. Note that when this bit goes high, it latches high until

it is unlatched by reading.

0x0

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