ADIN1300CCPZ-R7 datasheet(22/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 22 of 79

POWER-DOWN MODES

The ADIN1300 supports a number of power-down modes:

hardware, software, and energy detect power-down, and EEE

LPI mode. The lowest power mode is hardware power-down

mode where the device is turned fully off and is not accessible.

Hardware Power-Down Mode

Hardware power-down mode is useful when operation of the

ADIN1300 is not required and power must be minimized. The

ADIN1300 enters hardware power-down mode when the

RESET_N pin is asserted and held low. In this mode, all analog

and digital circuits are disabled, the CMU is disabled, the clocks

are gated off, and the only power is the leakage power of the

circuits. The management interface registers are not accessible

in this mode.

The following events occur in hardware power-down mode:

•

All analog and digital circuits are disabled.

•

The MAC interface output pins (output pins with respect

to the ADIN1300) are tristated. Internally, these pins have

a weak pull-down resistor, so these outputs are pulled low.

This assumes no external pull-up resistors connected to

these pins.

•

All internal clocks are gated off.

•

The PHY output clock (available on the GP_CLK pin) is

disabled.

•

The output reference clock (available on the CLK25_REF pin)

is disabled.

•

The management interface registers are not accessible.

Software Power-Down Mode

In software power-down mode, the ADIN1300 is powered down,

the management interface can be accessed, and the ADIN1300

can be configured. The ADIN1300 does not attempt to bring up

links until enabled.

Software power-down mode is useful when the device is being

configured by software before links are brought up. The

ADIN1300 can be configured to enter software power-down

mode after reset using the appropriate pull-up/pull-down

resistors on the LINK_ST pin and LED_0 pin, which sets the

default value of the SFT_PD bit, Address 0x0000, to 1. The

ADIN1300 also enters software power-down mode when the

SFT_PD bit is set to 1. In software power-down mode, the

analog and digital circuits are in a low power state. Typically, the

CMU is disabled, most clocks are gated off, and the clock for

the remaining digital circuitry runs at 25 MHz. Any signal or

energy on the MDI pins (MDI_x_x) is ignored and no links are

brought up. The management interface registers are accessible

and the device can be configured using software. If the

ADIN1300 is configured to output a 125 MHz clock on the

GP_CLK pin, the CMU is enabled and the power in this mode

is higher.

The following events occur in software power-down mode:

•

All analog transmit and receive circuits are disabled.

•

The MAC interface output pins (output pins with respect

to the ADIN1300) are driven to a known idle state. All

outputs except RXC/RX_CLK are driven low and

RXC/RX_CLK is driven high.

•

Most internal clocks are gated off.

•

The output reference clock (if enabled) is available on the

CLK25_REF pin.

•

The selected PHY output clock (if enabled) is available on

the GP_CLK pin.

•

The management interface registers are accessible.

The ADIN1300 exits software power-down mode when the

SFT_PD bit is cleared. At this point, the PHY attempts to bring

up links according to its configuration. For example, if

autonegotiation is enabled and all speeds are enabled, it advertises

all speeds and starts to send autonegotiation link pulses.

Energy Detect Power-Down Mode

In energy detect power-down mode, the ADIN1300 is powered

down but still monitors the line for signal energy. Typically, the

ADIN1300 enters this mode when there is no cable plugged in

and remains in this mode until a remote link partner is available.

Energy detect power-down mode can be enabled using the

appropriate pull-up/pull-down resistors on the LINK_ST pin

and LED_0 pin (see Table 23) or by setting the NRG_PD_EN

bit (PHY_CTRL_STATUS_2 register, Address 0x0015) to 1. When

the PHY is in normal operation (not software power-down) and

energy detect power-down mode is enabled, the PHY enters

energy detect power-down mode after a number of seconds of

silence on the line. This is a very low power mode in which the

analog and digital circuits are in a low power state. Typically,

the CMU is disabled and most clocks are gated off. If the

ADIN1300 is configured to output a 125 MHz clock on the

GP_CLK pin, the CMU is enabled and the power in this mode

is higher. The PHY monitors the line for signal energy and sends

a link pulse once every second. If signal energy is detected, the

PHY exits energy detect power-down mode and starts sending

link pulses.

The following events occur when in energy detect power-down

mode:

•

All analog and digital circuits are disabled.

•

Most internal clocks are gated off.

•

The output reference clock (if enabled) is available on the

CLK25_REF pin.

•

The selected PHY output clock (if enabled) is available on

the GP_CLK pin.

•

The management interface registers are accessible.

•

The PHY monitors the line for signal energy.

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