ADIN1300CCPZ-R7 datasheet(78/79 Pages) AD

78 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 78 of 79

PCB LAYOUT RECOMMENDATIONS

This is an overview of the key areas of interest during placement

and layout of the PHY and corresponding support components.

Take care when routing high speed interface signals to maximize

signal performance and ensure optimum EMC performance,

with a view to ensure critical signal traces are kept as short as

possible to minimize noise coupling.

PHY PACKAGE LAYOUT

The LFCSP has an exposed pad underneath the package that

must be soldered to the PCB ground for mechanical and thermal

reasons. For thermal impedance performance and to maximize

heat removal, use of a 4 × 4 array of thermal vias beneath the

exposed ground pad is recommended.

There are also two keep out areas on the top and bottom of the

exposed pad. The PCB land pattern must incorporate the exposed

ground paddle with vias and these two keep out areas in the

footprint. No PCB traces or vias can be used in either of the keep

out areas. The EVAL-ADIN1300FMCZ uses an array of 4 × 4

vias on a 0.75 mm grid arrangement, as shown in Figure 39.

The via pad diameter dimension is 0.02 in. (0.5015 mm) and

the finished drill hole diameter is 0.01 in. (0.2489 mm).

0.0295"

(0.75mm)

0.020"

(0.5105mm)

KEEPOUT

PIN 1

PIN 40

Figure 39. Exposed Paddle Via Array on EVAL-ADIN1300FMCZ

COMPONENT PLACEMENT

Prioritization of the critical traces and components helps simplify

the routing exercise. Place and orient the critical traces and

components first to ensure an effective layout with minimal

turns, vias, and crossing traces. For an Ethernet PHY layout, the

important components are the crystal and load capacitors, the

transformer on the MDI lines, and all bypass capacitors local to

the device. Prioritize these components and the routing to them.

Keep the PHY chip at least 1 in. away from the edge of the board.

The following sections provide more detail for each of the areas.

Crystal Placement and Routing

To ensure minimum current consumption and to minimize

stray capacitances, make connections between the crystal,

capacitors, and ground as close to the ADIN1300 as possible.

Magnetics Placement

Orient the magnetics and RJ45 in line with the MDI_x_x pins

from the PHY chip.

MDI, DIFFERENTIAL PAIR ROUTING

The MDI interface runs from the ADIN1300 PHY to the

transformer, and from there to the RJ45 connector. Traces

running from the MDI_x_x pins of the ADIN1300 to the

magnetics must be on the same side of the board, kept as short

as possible (ideally less than 1 in. in length), and individual trace

impedance of these tracks kept below 50 Ω, with differential

impedance of 100 Ω for each pair. The same recommendations

apply for traces running from the magnetics to the RJ45

connector. Keep impedances constant throughout because any

discontinuities may affect signal integrity.

Each pair must be routed together, trace widths kept the same

throughout, trace lengths kept equal where possible, and avoid

any right angles on these traces (use curves in traces or 45° angles).

Avoid stubs on all signal traces. Where possible, route traces on

the same layer.

Route traces over a continuous reference plane with no

interruptions to reduce inductance.

Where possible, ensure a solid return path underneath all signal

traces. Avoid routing signal traces across plane splits.

TRACES

RUN PARALLEL

THROUGHOUT

AVOID

STUBS

GROUND OR POWER

GROUND

OR POWER

AVOID CROSSING

POWER OR GND

PLANES

Figure 40. Things to Avoid when Routing Differential Pairs

MAC INTERFACE PINS

Keep trace lengths as short as possible. Route traces with an

impedance of 50 Ω to ground.

POWER AND GROUND PLANES

From a PCB layout point of view, it is important to place the

decoupling capacitors as close as possible to the power and GND

pins to minimize the inductance.

Magnetics Module Grounding

A split ground plane under the transformer minimizes noise

coupling across the transformer and between adjacent coils within.

Ensure a physical separation of the ground planes underneath

the transformer. Make the width of this separation at least 100 mil.

RJ45 Module Grounding

For optimal EMC performance, it is recommended to use a

metal shielded RJ45 connector with the shield connected to

chassis ground. There must be an isolation gap between the

chassis ground and the PHY IC ground with consistent

isolation across all layers.

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