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FT93x Datasheet Embedded Microcontroller Datasheet

Version 1.5

Document Reference No.: BRT_000051

Clearance No.: BRT#049

4.4

128kB Flash Memory

The internal 128kB Flash memory is used to store a bootloader or user application for the FT93x series. It

is a high performance and low power consumption memory that supports up to 80MHz serial clock. The

system will perform memory copy from Flash memory to CPU program memory automatically after

system power on.

4.5

Boot Sequence

After the initial memory copy completes, the CPU jumps to program memory location zero. This may be

the start of the user’s application which is stored in advance in the flash memory, or a bootloader, which

allows modification of the program memory via UART or USB as an example.

The option of a bootloader is a special purpose routine in the FT93x Series embedded microcontroller. It

is a small routine stored in the flash memory. Typically, the bootloader is 1kB to 4kB in size, and resides

at the top of the memory.

4.6

Interrupt

The FT93x interrupt controller handles 32 interrupt inputs. When an interrupt occurs, the Interrupt

Service Route (ISR) will process this event via the CPU. The ISR vector range is from 0 to 31, which

corresponds to interrupt 0 to 31. See Table 4-1 for further information.

Each interrupt shall be assigned the interrupt vector number and priority before use. By default, the

highest priority interrupt is interrupt 0, and the lowest is interrupt 31. However, the interrupt priority can

be rearranged by register settings and also allows multiple interrupts at the same priority.

To prevent the loss and delay of high priority interrupts, the FT93x series uses nested interrupts if

enabled. Nested interrupts allow interrupt requests of a high priority to pre-empt interrupt requests of a

lower priority. The FT93x series supports up to 16-levels deep nested interrupts.

The interrupt controller has a global interrupt mask bit to temporarily block all interrupts. If this bit is set

to “1”, then with the exception of an interrupt assigned priority as “0”, which is a non-maskable interrupt

(NMI) input, all interrupts are masked.

See Table 4-1 for the FT93x series default interrupt priority.

Peripherals of Interrupt

Interrupt Vector Index

Default Priority

Power Management

0 (NMI)

Reserved

USB2.0 Device Controller

Reserved

SD Host Controller

Mailbox Source

Mailbox Destination

UART 3

SPI Master

SPI Slave

Reserved

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