FT930Q-R datasheet(35/65 Pages) BRIDGETEK

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FT93x Datasheet Embedded Microcontroller Datasheet

Version 1.5

Document Reference No.: BRT_000051

Clearance No.: BRT#049

4.9

Real Time Clock

The Real Time Clock (RTC) runs off a dedicated 32 kHz oscillator with its own power rail which can be

connected to a separate battery.

4.9.1 Features



Two clock sources, PCLK and CLK32KHZ



Built-in Clock Stabilizer for CLK32KHZ



Records system sleep time



Supports Date and Time format in BCD



Counts Second, Minute, Hour, Day, Date of the Month, Month and Year with Leap-Year

Compensation Valid up to 2199



Supports two configurable Time-of-Day Alarms



Supports 1Hz and 32768Hz clock outputs



Supports interrupt with 4 configurable events



Supports Oscillator Stop Flag with both external trigger and internal auto detection



Supports On-Chip Digital Trimming with Auto Calibration

4.10

One-Wire Debugger Interface

The Debugger interface provides the capability over a One-Wire half duplex serial link, to access memory

mapped address space, such as the FT93x flash memory, program memory, data memory, and I/O

memory. However, there is no transfer capability from any of the internal memory to the debugger

interface.

4.10.1 Features



Single wire half duplex link that has one Start, eight Data and one Stop bit at a 1M bit/s rate.



Supports debugger command read / write operation with variable data transfer.



Supports CHIP ID read out.



Supports checksum check by Flash memory operation.



Supports CPU software debugging to execute Run, Stop, Step, Halt, Set software breakpoint, etc.

operations.



Use semaphore flag to control resource allocated by CPU or Debugger.

4.11

SPI Interface

The FT93x series contains both SPI Master and SPI Slave controllers. SPI is a full duplex serial interface

designed to handle multiple masters and slaves connected to a given bus.

4.11.1 Features



Maximum SPI data bit rate 25MHz in master and slave modes.



Full duplex synchronous serial data transfer.



Compliant with SPI specification, supporting four transfer formats.



SPI master supports Single, Dual, and Quad SPI transfer.



SPI Slave support Single transfer only.



Support SPI mode and FIFO mode operations.



Multi-master system supported.



Support bus error detection.



SPI master can address up to 4 SPI slave devices.



Support 64 Bytes receiver and 64 Bytes transmitter FIFO respectively.

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