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FT93x Datasheet Embedded Microcontroller Datasheet

Version 1.5

Document Reference No.: BRT_000051

Clearance No.: BRT#049

Function

Address Memory Range

Comment

UART 2 registers

0x10540

0x1054F

UART 3 registers

0x10550

0x1055F

Timers (include Watchdog)

registers

0x10560

0x1056F

PWM registers

0x105B0

0x105EF

Registers: B access

FIFO: W access

SD Host Controller registers

0x10600

0x107FF

Flash Controller registers

0x10800

0x108BF

Reserved

0x108C0

0x130FF

Table 4-2 FT93x Series I/O Memory Mapping

[Note] DW/W/B is the lengths of register operations.

DW:

Double Word (32-bit)

Word (16-bit)

Byte (8-bit)

4.8

USB2.0 Device Contoller

The USB 2.0 Device controller is fully compliant with the USB2.0 specification. There is also an option to

enable a battery charger detection (BCD) feature on the upstream port, which can identify whether the

connected downstream port supports SDP, CDP or DCP charging function. Battery charge detection allows

the USB Device to determine if higher currents may be available from the USB connection for rapid

battery charging.

When the D2XX hardware engine is enabled, the USB Device is under the controller of the D2XX

hardware engine, the data transfer to USB from the FT93x is via a FIFO interface.

4.8.1 Features



Supports data transfer at hi-speed (480 Mbit/s) and full-speed (12 Mbit/s).



Software configurable EP0 control endpoint size 8-64 bytes.



Software configurable 15 In/Out endpoints.



EP1-EP15 has double buffering with 8,128B buffers.



Supports Isochronous/Interrupt/Control/Bulk data transfers.



Max endpoint packet sizes up to 1024 bytes.



Supports VBUS detection.



Supports suspend and resume power management functions.



Supports remote wakeup feature.



Supports Battery Charging specification revision 1.2.

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