L9965P datasheet(82/104 Pages) STMICROELECTRONICS

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3.16

Software reset (SW_RST)

It is possible to reset the configuration of the device sending a SW_RST sequence.

Once triggered, the software reset procedure resets all SPI registers to their default values, including diagnostic

fault flags and lock protected bit fields.

To reset the device configuration, the following procedure shall be implemented:

1. MCU writes 0xE1 into the SPECIAL_KEY register to enter partial reset mode.

2. MCU writes 0x1E into the SPECIAL_KEY register to confirm the reset.

Frames must be sent exactly in this sequence, otherwise registers will not be reset.

User software can eventually trigger a redownload of the configuration from the non-volatile memory (NVM).

Note:

Since the NVM is redownloaded at each wake-up, the new configuration eventually applied shall be pushed into

the memory with a “write” instruction. Otherwise, the old configuration will be restored at the next wake-up event.

3.17

Configuration integrity check (CONF_CRC)

To guarantee the integrity over time of NVM downloaded trimming/calibration and configuration data, both safety

relevant and latent register content is automatically and cyclically checked against corruption within NORMAL

mode. This is possible because local register data is provided with a CRC signature, that is checked every

tCONF_CRC_PERIOD, while no operation on the NVM is being performed (NVM circuit in reset state).

The duration of the calculation is tCONF_CRC_TIME.

In case of check failure, the following actions are performed:

•

In case trimming/calibration data has failed the CRC signature check, CYC_TRIM_CAL_CRC_FAIL latch is

set (clear-upon-read).

•

In case IC configuration data has failed the CRC signature check, CYC_CFG_CRC_FAIL latch is set

(clear-upon-read).

•

In both cases, the deployment is inhibited and FAULTN is asserted but there is no interruption/inhibition of

other IC functionalities.

In case of permanent data corruption, failure latch set pulse occurs every tCONF_CRC_PERIOD.

The local register CRC signature is managed in the following way:

•

Every time NVM data is downloaded into local registers (either automatically or user-driven), a CRC

signature is refreshed as well and written in the CLIENT_CONFIG_CRC bit field.

•

Every time the user changes the local register data, the corresponding CRC signature is not automatically

updated, thus a CRC check failure is expected at the next execution cycle. By the way, as the user triggers

the NVM upload and refresh operation, after the NVM sector CRC has been automatically updated, the

local register CRC signature is updated accordingly and no further CRC check failure is expected.

The integrity check can be disabled by setting CYC_CRC_DIS = 1. After the diagnostic has been disabled, it is

still possible to clear-upon-read both CYC_TRIM_CAL_CRC_FAIL and CYC_CFG_CRC_FAIL. Disabling such

diagnostic can be useful to mask systematic CRC failure detection when updating IC configurations. The

deployment inhibition is removed. On the other hand, leaving it enabled while updating register configurations

may be used as a fault injection strategy to assess the correct functionality of the diagnostics.

3.17.1

Configuration integrity check electrical parameters

All parameters are tested and guaranteed in the following conditions, unless otherwise noted: all supplies

according to the Table 3; TJ according to the Table 2.

Table 88. Configuration integrity check characteristics

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

tCONF_CRC_PERIOD

Configuration integrity check period

Tested by SCAN

tCONF_CRC_TIME

Configuration integrity check time

Tested by SCAN

175

190

210

µs

3.18

Non-volatile memory (NVM)

The IC allows saving key configuration parameters in the internal NVM.

L9965P

Functional description

DS14702 - Rev 4

page 82/104

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