L9965P datasheet(28/104 Pages) STMICROELECTRONICS

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3.6.1.2

FENH/FENL integrity check

The IC provides diagnostics embedded in the decoder stage aimed at verifying the integrity of the trigger input

signals. Their behavior depends on the corresponding signaling mode and configuration:

•

In PWM mode (FENx_MODE = 1), the signal integrity is continuously monitored by an internal timer

measuring the time interval between rising edges

–

Signals whose frequency lies within fFENx_PWM_FREQ_TH_xL/fFENx_PWM_FREQ_TH_xH limits are

considered valid and their duty-cycle is furtherly evaluated by the decoder to determine whether the

pulse corresponds to a fire/no-fire/invalid command (see the Figure 11).

–

Signals whose frequency is higher than fFENx_PWM_FREQ_TH_xH are considered invalid and the

corresponding FENH_HIGH_FREQ / FENL_HIGH_FREQ latch in FENX_INTEGRITY_STATUS

–

Signals whose frequency is lower than fFENx_PWM_FREQ_TH_xL but still higher than

fFENx_PWM_FREQ_TH_xT are considered invalid and the corresponding FENH_LOW_FREQ /

FENL_LOW_FREQ latch in FENX_INTEGRITY_STATUS register is set (see the Figure 12).

–

If the signals frequency drops below fFENx_PWM_FREQ_TH_xT, a timeout condition is acknowledged

and the corresponding FENH_PWM_TIMEOUT / FENL_PWM_TIMEOUT latch in

FENX_INTEGRITY_STATUS register is set (see the Figure 11).

–

The above requirements on frequency can be seen also as requirements on times, as shown in the

Figure 13.

–

The internal timeout to check the PWM frequency starts as soon as the FENx_MODE bit is set to 1

and is reset on each rising edge (see the Figure 11 and Figure 12).

–

“No-fire” and “invalid” signals decrement the NFENx_FAULT_PERIOD fault counter by 1, while “fire”

signals increment the NFENx_FAULT_PERIOD by 1. In case of “timeout”, the NFENx_FAULT_PERIOD

counter is reset and restarts from 0.

•

When in level mode (FENx_MODE = 0), the signal integrity check can be enabled by setting

FENH_INT_CHECK_EN = 1/FENL_INT_CHECK_EN = 1

–

In this scenario, the IC locks to the FAULTN signal to perform the FENH/FENL integrity check. An

internal tFENx_TIMEOUT is started upon FAULTN rising edge and reset after two consecutive edges on

the corresponding FENx line.

–

If the timeout expires, the corresponding FENH_LEV_TIMEOUT/FENL_LEV_TIMEOUT latch in the

FENX_INTEGRITY_STATUS register is set (see the Figure 14). Once latched, the fault is cleared,

and the correspondent timeout is reset, when the FENH_LEV_TIMEOUT/FENL_LEV_TIMEOUT bit is

read.

–

When the low power strategy is implemented, to detect a possible fault due to timeout expiration, the

IC shall be kept awake for a time greater than tFENx_TIMEOUT. This could be done simply by keeping

the CWUP pin high for more than tFENx_TIMEOUT, and/or enabling VRCM check and pyro outputs

leakage test.

•

Alternatively, a manual integrity check can be performed by the MCU, toggling the FENH and FENL input

signals and looking at the FENH_ECHO and FENL_ECHO status bits in the FENX_INTEGRITY_STATUS

L9965P

Functional description

DS14702 - Rev 4

page 28/104

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