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LMKDB1104FS Scheda tecnica(PDF) 23 Page - Texas Instruments |
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LMKDB1104FS Scheda tecnica(HTML) 23 Page - Texas Instruments |
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23 / 133 page  6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLOCK INPUT REQUIREMENTS VIN, cross Clock input crossing point voltage 100 1400 mV DCIN Clock input duty cycle 45 55 % VIN Differential clock input amplitude (half of differential peak-peak voltage) f0 ≤ 300 MHz 200 2000 mV 300 MHz < f0 ≤ 400 MHz 250 2000 mV dVIN/dt Clock input slew rate Measured from –150 mV to +150 mV on the differential waveform 0.6 V/ns CLOCK OUTPUT CHARACTERISTICS - 100 MHz 85 Ω PCIe VOH,AC Output voltage high Output swing programmed to 750mV. DB2000QL AC test load(6) 670 820 mV VOL,AC Output voltage low –100 100 mV Vmax,AC Output max voltage (including overshoot) 670 920 mV Vmin,AC Output min voltage (including undershoot) –100 100 mV VOH,AC Output voltage high Output swing programmed to 950mV 870 1020 mV VOL,AC Output voltage low –100 100 mV Vmax,AC Output max voltage (including overshoot) 870 1120 mV Vmin,AC Output min voltage (including undershoot) –100 100 mV VOH,DC Output voltage high with DC test load DB2000QL DC test load(2) 225 270 mV VOL,DC Output voltage low with DC test load 10 150 mV Vovs,DC Output overshoot voltage with DC test load 75 mV Vuds,DC Output undershoot voltage with DC test load –75 mV Zdiff Differential output impedance Measured at VOL/VOH, VDD = 3.3 V 80.75 85 89.25 Ω Measured at VOL/VOH, VDD = 1.8 V 81 85 90 Ω Zdiff- crossing Differential output impedance - crossing Measured during transition 68 85 102 Ω dV/dt Output slew rate Measured from –150 mV to +150 mV on the differential waveform. Lowest slew rate(6) (7) 1.5 2.2 V/ns Measured from –150 mV to +150 mV on the differential waveform. Low slew rate(6) (7) 1.8 2.6 V/ns Measured from –150 mV to +150 mV on the differential waveform. High slew rate (default)(6) (7) 2 2.9 V/ns Measured from –150 mV to +150 mV on the differential waveform. Highest slew rate(6) (7) 2.4 4 V/ns ∆dV/dt Rising edge rate to falling edge rate matching DB2000QL AC test load(6) 10 % DCD Duty cycle distortion Measured on the differential waveform. Input duty cycle = 50%(6) –1 1 % Vcross,AC Absolute crossing point voltage DB2000QL AC test load(6) 250 550 mV Vcross,DC Absolute crossing point voltage DB2000QL DC test load(2) 130 200 mV ∆Vcross,A C Variation of Vcross over all clock edges DB2000QL AC test load(6) 140 mV ∆Vcross- DC Variation of Vcross over all clock edges DB2000QL DC test load(2) 35 mV www.ti.com LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS LMKDB1112, LMKDB1120, LMKDB1120FS SNAS855G – NOVEMBER 2023 – REVISED MAY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS |
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