LMKDB1104FS datasheet(13/133 Pages) TI2

13 / 133 page

Table 5-3. LMKDB1112 Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME(2) (3)

NO.

^/vOE4#/SBI_CLK

A10

Active low input to control CLK4 or SBI clock input pin. SBI_EN pin controls function of this

pin.

OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI clock input.

^OE5#

Active low input to control CLK5. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE6#

Active low input to control CLK6. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^/vOE7#/SBI_IN

K10

Active low input to control CLK7 or SBI data input pin. SBI_EN pin controls function of this

pin.

OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI data input.

^OE8#

Active low input to control CLK8. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE9#

Active low input to control CLK9. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE10#/SHFT_LD#

Active low input to control CLK10 or SBI active low shift register load pin. SBI_EN pin

controls function of this pin. OE mode with internal pullup: 0 = Active output, 1 = Inactive

output.

Side-Band Mode with internal pulldown: SBI latch register input.

^OE11#

Active low input to control CLK11. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^PWRGD/PWRDN#

Power Good/Power Down Active Low. Multifunctional input pin. Internal pullup resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which

controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode

vSBI_EN

SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin L8, L10 and E11 function as OE pins. High

at power-up = SBI interface enabled.

Pin L8, L10 and E11 function as SBI interface pins. SMBus and other OE pins remain

functional.

^vSADR1_tri

SMBus Address 3-level input pin. Internal pullup and pulldown resistors.

^vSADR0_tri

SMBus Address 3-level input pin. Internal pullup and pulldown resistors.

^SLEWRATE_SEL

LP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.

LOS#

Loss of Input Clock Signal Active Low. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.

SMB_DATA

I/O

SMBus Data. Requires external pullup resistor. No connect if unused.

SMB_CLK

SMBus Clock. Requires external pullup resistor. No connect if unused.

B2, B6, B9,

D9, E2, F9,

G2, J2, J5, J7,

J9, K3

No connect.

(1)

I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect

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SNAS855G – NOVEMBER 2023 – REVISED MAY 2026

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