LMKDB1104FS datasheet(1/133 Pages) TI2

Il numero della parte	LMKDB1104FS

Spiegazioni elettronici	LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family

PDF	133 Pages

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Produttore elettronici	TI2 [Texas Instruments]

Homepage	https://www.ti.com

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LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family

1 Features

• LP-HCSL clock buffer and clock MUX that support:

– PCIe Gen 1 to Gen 7

– CC (Common Clock) and IR (Independent

Reference) PCIe architectures

– Input clock with or without SSC

• Intel DB2000QL and DB1206 compliant:

– All devices meet DB2000QL specifications

– LMKDB1120 is pin-compatible to DB2000QL

– LMKDB1112 is pin-compatible to DB1206

• Extremely low additive jitter:

– 31fs maximum 12kHz to 20MHz RMS additive

jitter at 156.25MHz

– 13fs maximum additive jitter for PCIe Gen 4

– 5fs maximum additive jitter for PCIe Gen 5

– 3fs maximum additive jitter for PCIe Gen 6

– 2.1fs maximum additive jitter for PCIe Gen 7

• Fail-safe input

• Fail-safe outputs (LMKDB1120FS, LMKDB1108FS

and LMKDB1104FS only)

• Flexible power-up sequence

• Automatic output disable

• Individual output enable

• SBI (Side Band Interface) for high-speed output

enable or disable

• LOS (Loss of Signal) input detection

• 85Ω or 100Ω output impedance

• 1.8V / 3.3V ± 10% power supply

• –40°C to 105°C ambient temperature

2 Applications

• High Performance Computing

• Server Motherboard

• NIC/SmartNIC

• Hardware Accelerator

3 Description

The LMKDB devices are a family of extremely-low-

jitter LP-HCSL buffers that support PCIe Gen 1 to

Gen 7 and are DB2000QL compliant. The devices

provide flexible power-up sequence, fail-safe inputs,

fail-safe outputs, individual output active and inactive

pins, loss of input signal (LOS) detection and

automatic output disable features, as well as excellent

power supply noise rejection performance.

Both 1.8V and 3.3V supply voltages are supported.

For LMKDB1120, 1.8V power supply saves 250mW

power compared to 3.3V.

Package Information

PART NUMBER

PACKAGE(1)

PACKAGE SIZE(2)

LMKDB1120 /

LMKDB1120FS

NPP (TLGA, 80)

6mm × 6mm

LMKDB1113 (3)

REJ (VQFN, 56)

7mm × 7mm

LMKDB1112

ZSF (LGA, 64)

5mm × 5mm

LMKDB1108 /

LMKDB1108FS

RKP (VQFN, 40)

5mm × 5mm

LMKDB1104 /

LMKDB1104FS

REX (VQFN, 28)

4mm × 4mm

LMKDB1102

REY (VQFN, 20)

3mm × 3mm

(1)

For all available packages, see Section 13.

(2)

The package size (length × width) is a nominal value and

includes pins, where applicable.

(3)

Preview only.

LMKDB family

PCIe Clock Buffer

SMBus

Control

OE#

Control

PCIe PHY

LP-HCSL

PCIe PHY

PCIe Device

Side-Band

Interface

Control Interface

PCIe Clock Source

Typical Application

LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS

LMKDB1112, LMKDB1120, LMKDB1120FS

SNAS855G – NOVEMBER 2023 – REVISED MAY 2026

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Codice articolo simile - LMKDB1104FS

Produttore elettronici	Il numero della parte	Scheda tecnica	Spiegazioni elettronici
Texas Instruments	LMKDB1104FS	5Mb / 95P	LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family REVISED AUGUST 2025
	LMKDB1104FS	6Mb / 126P	LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family REVISED NOVEMBER 2025
	LMKDB1104FS85	5Mb / 95P	LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family REVISED AUGUST 2025
	LMKDB1104FS85	6Mb / 126P	LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family REVISED NOVEMBER 2025
	LMKDB1104FS85	2Mb / 69P	LMKDB12xx PCIe Gen 1 to Gen 7 Ultra Low Jitter 2 Input Clock MUX REVISED APRIL 2026

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