LMKDB1104FS datasheet(41/133 Pages) TI2

41 / 133 page

8.3.3.3 OE Control

OE (Output Enable) can enable or disable a certain output. Three types of OE controls are supported: OE pin,

OE register bit through SMBus, and OE control through SBI. The three controls follow the AND logic. An output

is enabled only if all three controls enable that output. If any control disables that output, that output is disabled.

8.3.3.4 Automatic Output Disable

Automatic Output Disable (AOD) is enabled by default, and can be disabled through SMBus. When input clock

becomes invalid and LOS# is active, output clocks are muted to low/low (OUTx_P = Low, OUTx_N = Low).

Before LOS# is active and after input clock becomes invalid (because LOS detection takes time), output clocks

stay at a steady state following the last input state. For example, if the input clock stopped at low/high, then

output clocks first stay at low/high, then muted to low/low once LOS# is active.

8.3.3.5 LOS Detection

LOS (Loss Of input Signal) detects whether the clock input is valid or not. When input clock is valid, LOS#

At power-up, the LOS# pin is kept low until input is detected valid. Therefore, the LOS# pin can be used for the

timing of OE# insertion and other operations.

The LOS# signal is only effective if PWRGD/PWRDN# pin is high. If this pin is low, then LOS# is low regardless

of input validness

8.3.4 Output Features

8.3.4.1 Double Termination

For regular PCIe applications, LP-HCSL outputs do not require external termination, but the LMKDB family does

support double termination (this is uncommon). In that case, an external 50Ω termination is placed and the swing

is halved. This results additional power consumption as well due to 50Ω termination to ground on the output.

8.3.4.2 Programmable Output Slew Rate

The LMKDB family offers slew rate control options through SMBus and pin modes. The pin mode option is

global slew rate control for all the outputs. SMBus slew rate control supports programmable output slew rate for

each individual output. The slew rate is heavily dependent on trace characteristics including trace width, copper

thickness, substrate height, dielectric constant, and loss tangent.

LMKDB slew rate control settings are tested with PCIe test load shown in Figure 7-1.

8.3.4.2.1 Slew Rate Control through Pin

The LMKDB11xx offer a global slew rate control pin for specific devices. Refer to Section 5 for details on slew

rate pin on each device. The pin can be set to low for slow slew rate setting and high for high slew rate. Table

8-2 provides more information on the slew rate control option through pin mode.

Table 8-2. Pin Mode Slew Rate Control

Pin Status

Slew Rate Setting

Slew Rate Range (V/ns)

Low

1.8 - 2.6

High

2 - 2.9

8.3.4.2.2 Slew Rate Control Through SMBus

The LMKDB11xx has 16 different slew rates options that can be assigned to the outputs. 0x0 is the fastest slew

rate setting and 0xF is the slowest slew rate setting. To set the slew rate of each output, follow these steps:

1. There are four different registers, SLEWRATE_OPT#, that can store up to four different slew rates. Select

your desired slew rates by assigning a value from 0x0 (fastest) to 0xF (slowest) to each SLEWRATE_OPT#

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LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS

LMKDB1112, LMKDB1120, LMKDB1120FS

SNAS855G – NOVEMBER 2023 – REVISED MAY 2026

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