LMKDB1104FS datasheet(100/133 Pages) TI2

100 / 133 page

The maximum PCIe Gen 5 additive jitter allowed for the buffer is sqrt(502 – 452) = 21 fs. According to the

Specifications under the Electrical Characteristics table, the additive PCIe Gen 5 jitter under Common Clock

and ≥3.5V/ns input slew rate test condition is 13fs maximum, well below 21fs requirement. Therefore, the

LMKDB1120 (20 outputs) can be used for PCIe Gen 5 clock distribution.

Similarly, the maximum 12kHz to 20MHz additive jitter allowed at 156.25MHz is sqrt(1002 – 902) = 43fs.

According to the Specifications under the Electrical Characteristics table, the 12kHz to 20MHz additive jitter at

156.25MHz is 31fs maximum, well below the 43fs requirement. Therefore, the LMKDB1108 (8 outputs) can be

used for Ethernet clock distribution.

10.2.3 Application Curves

The following plots are example phase noise plots before and after using the LMKDB at 156.25MHz,

respectively. The LMKDB clock buffer adds a 22fs (typical) jitter from 12kHz to 20MHz. All LMKDB devices

have very similar performance.

To better understand jitter and how the additive jitter of the LMKDB resulted in 22fs refer to Timing is Everything:

How to measure additive jitter TI blog post.

Figure 10-2. Input Source at 156.25MHz (12kHz -

20MHz)

See Note 1 and 2 in Graph Notes table

Figure 10-3. LMKDB11xx/120x Phase Noise /

Output Jitter at 156.25MHz (12kHz - 20MHz)

Table 10-2. Graph Notes

NOTE

(1)

The typical RMS jitter values in the plots show the total output RMS jitter (JOUT) for each frequency and the source clock RMS

jitter (JSOURCE). From these values, the Additive RMS Jitter can be calculated as: JADD = SQRT(JOUT 2 – JSOURCE 2).

(2)

JADD at 156.25MHz = SQRT(33.92- 25.82) = 22.0 fs

10.3 Power Supply Recommendations

Place a 0.1μF capacitor close to every power supply pin. To minimize noise on VDDA, VDD_IN0 and VDD_IN1,

place a 2.2Ω resistor next to the pins. All supply pins can be grouped onto one power rail. TI recommends a

Ferrite Bead and a 10µF capacitor to GND for the entire chip. Figure 10-4 and Figure 10-5 shows an example

power schematic.

LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS

LMKDB1112, LMKDB1120, LMKDB1120FS

SNAS855G – NOVEMBER 2023 – REVISED MAY 2026

www.ti.com

100

Submit Document Feedback

Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS

LMKDB1104FS Scheda tecnica(PDF) 100 Page - Texas Instruments