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LMKDB1104FS Scheda tecnica(PDF) 57 Page - Texas Instruments

Il numero della parte LMKDB1104FS
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  133 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LMKDB1104FS Scheda tecnica(HTML) 57 Page - Texas Instruments

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Table 9-25. R92 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
SLEWRATE_OPT_4
R/W
Fh
There are four register assignments each storing a slew rate value
(chosen out of 16 available slew rate values). This register bits relate
to the 4th option. Go to Programmable Output Slew Rate section for
more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
3:0
SLEWRATE_OPT_3
R/W
6h/Ah
There are four register assignments each storing a slew rate value
(chosen out of 16 available slew rate values). This register bits relate
to the 3rd option. Go to Programmable Output Slew Rate section for
more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6 (Default for LMKDB1120FS)
7h = 7
8h = 8
9h = 9
Ah = 10 (Default for LMKDB1120)
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
9.1.24 R98 Register (Offset = 62h) [Reset = 00h]
R98 is shown in Table 9-26.
Return to the Summary Table.
Table 9-26. R98 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLEWRATE_SEL_CLK7_
LSB
R/W
0h
LSB CLK7 slew rate select
6
SLEWRATE_SEL_CLK6_
LSB
R/W
0h
LSB CLK6 slew rate select
5
SLEWRATE_SEL_CLK5_
LSB
R/W
0h
LSB CLK5 slew rate select
4
SLEWRATE_SEL_CLK4_
LSB
R/W
0h
LSB CLK4 slew rate select
3
SLEWRATE_SEL_CLK3_
LSB
R/W
0h
LSB CLK3 slew rate select
www.ti.com
LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS
LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855G – NOVEMBER 2023 – REVISED MAY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS



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