R5F572TFGDFP datasheet(109/120 Pages) RENESAS

109 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 109 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

2.11

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Note:

The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,

and Vdet2 for the POR/ LVD.

Figure 2.67

Power-on Reset Timing

Table 2.52

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Voltage detection level

Power-on reset (POR)

VPOR

2.46

2.58

2.70

Figure 2.67

Voltage detection circuit

(LVD0)

Vdet0_1

4.04

4.22

4.40

Figure 2.68

Vdet0_2

2.71

2.83

2.95

Voltage detection circuit

(LVD1)

Vdet1_0

4.39

4.57

4.75

Figure 2.69

Vdet1_1

4.29

4.47

4.65

Vdet1_2

4.14

4.32

4.50

Vdet1_3

2.81

2.93

3.05

Vdet1_4

2.76

2.88

3.00

Voltage detection circuit

(LVD2)

Vdet2_0

4.39

4.57

4.75

Figure 2.70

Vdet2_1

4.29

4.47

4.65

Vdet2_2

4.14

4.32

4.50

Vdet2_3

2.81

2.93

3.05

Vdet2_4

2.76

2.88

3.00

Internal reset time

Power-on reset time

tPOR

—

13.7

—

Figure 2.67

LVD0 reset time

tLVD0

—

0.70

—

Figure 2.68

LVD1 reset time

tLVD1

—

0.57

—

Figure 2.69

LVD2 reset time

tLVD2

—

0.57

—

Figure 2.70

Minimum VCC down time

tVOFF

200

—

µs

Figure 2.67,

Figure 2.68

Response delay time

tdet

—

200

µs

Figure 2.67 to

Figure 2.70

LVD operation stabilization time (after LVD is enabled)

Td(E-A)

—

µs

Figure 2.69,

Figure 2.70

Hysteresis width (LVD1 and LVD2)

V LVH

—80

—

Internal reset signal

(Low is valid)

VCC

tVOFF

tdet tPOR

tdet

tPOR

tdet

VPOR

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