ORSPI4 datasheet(71/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

SPIA_RX32_ADDR_1[2:0]

FPGA

→ Core FIFO read address.

SPIA_RX32_DATA_1[31:0]

Core

→FPGA FIFO read data.

SPIA_RX32_BE_1[3:0]

Core

→FPGA Byte enables

Bit 3 - Byte enable for SPIA_RX32_DATA_1[31:24]

Bit 2 - Byte enable for SPIA_RX32_DATA_1[23:16]

Bit 1 - Byte enable for SPIA_RX32_DATA_1[15:8]

Bit 0 - Byte enable for SPIA_RX32_DATA_1[7:0]

SPIA_RX32_CTL_1

Core

→FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX32_DATA_1 bus contains

the port ID.

SPIA_RX32_SOP_1

Core

→FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.

SPIA_RX32_EOP_1

Core

→FPGA End of Packet Indicator. A ‘1’ indicates end of packet.

SPIA_RX32_ERR_1

Core

→FPGA Error. A ‘1’ indicates an error in the current word.

SPIA_RX32_FIFO_EMPTY_1 Core

→FPGA FIFO Empty ﬂag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[1]

software register bit in address 0x30920. When this bit is set to ‘0’, (default)

the empty ﬂag indicates truly empty.

When this bit is set to ‘1’, the empty ﬂag indicates that the FIFO is 1/4 full -1.

ASTOP_ON_EOP1

FPGA

→ Core Timing control for handling end of packet.

SPIA_RX32_CLK_1

FPGA

→ Core FIFO read clock.

SPIA_RX32_RD_1

FPGA

→ Core FIFO read enable.

SPIA_RX32_ADDR_2[2:0]

FPGA

→ Core FIFO read address.

SPIA_RX32_DATA_2[31:0]

Core

→FPGA FIFO read data.

SPIA_RX32_BE_2[3:0]

Core

→FPGA Byte enables

Bit 3 - Byte enable for SPIA_RX32_DATA_2[31:24]

Bit 2 - Byte enable for SPIA_RX32_DATA_2[23:16]

Bit 1 - Byte enable for SPIA_RX32_DATA_2[15:8]

Bit 0 - Byte enable for SPIA_RX32_DATA_2[7:0]

SPIA_RX32_CTL_2

Core

→FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX32_DATA_2 bus contains

the port ID.

SPIA_RX32_SOP_2

Core

→FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.

SPIA_RX32_EOP_2

Core

→FPGA End of Packet Indicator. A ‘1’ indicates end of packet.

SPIA_RX32_ERR_2

Core

→FPGA Error. A ‘1’ indicates an error in the current word.

SPIA_RX32_FIFO_EMPTY_2 Core

→FPGA FIFO Empty ﬂag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[2]

software register bit in address 0x30920. When this bit is set to ‘0’, (default)

the empty ﬂag indicates truly empty.

When this bit is set to ‘1’, the empty ﬂag indicates that the FIFO is 1/4 full -1.

ASTOP_ON_EOP2

FPGA

→ Core Timing control for handling end of packet.

SPIA_RX32_CLK_2

FPGA

→ Core FIFO read clock.

SPIA_RX32_RD_2

FPGA

→ Core FIFO read enable.

Table 12. SPIA Core Receive FPGA Interface in 32-Bit Mode (Continued)

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

Note: For SPIB replace A with B

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