ORSPI4 datasheet(8/263 Pages) LATTICE

8 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

• Automatic idle generation

– When no data for a given channel is available for transmit

– If the receiver on other end of the link is “satisﬁed” for this channel

• Automatic training pattern and idle deletion in receive path

• Low-power, high performance ASIC LVDS I/Os compliant with EIA

®-644

– I/O buffers support hot insertion

– I/O buffers proven to operate at over 900 MHz rates (Lattice ORLI10G FPSC uses same LVDS buffers)

– On-chip center tap termination for common mode noise reduction

• Conﬁguration options as suggested in the OIF-SPI4-02.0 standard are supported to conﬁgure parameters such

as maximum burst size, calendar length, length of training sequence, etc.

• Support for three forms of loopback:

– High-speed near end loopback which involves looping back data from the high-speed transmit block serial

output to the high-speed receive block serial input. All of the logic up to the LVDS buffers is included in the

loopback path. The LVDS buffers are bypassed

– Far end loopback which involves looping back the 128-bit output data from high-speed receive block to the

128-bit input of the high-speed transmit block. Data is received at the high-speed SPI4 RX interface and

transmitted at the SPI4 TX interface. The transmit protocol, receive protocol and DPRAM blocks are

bypassed. This works for both static and dynamic alignment modes.

– Low-speed near end loopback which excludes the high-speed blocks from the loopback path. This involves

sourcing data from the FPGA, looping back the output of the transmit protocol block into the receive protocol

block and observing data at the core-FPGA boundary

• Support for several SPI4 debug options:

– Under software control, DIP-4 errors can be forced by inverting the DIP-4 parity bits

– DIP-2 errors can be forced by inverting the DIP-2 parity bits

– Eight-bit counters are provided for counting DIP-4 and DIP-2 errors

• SPI4 Status Reporting Capabilities:

– Status information is reported through status registers.

– Most conditions can also cause an alarm (interrupt) to be generated

– DIP-4, DIP-2 errors

– Deskew error from high-speed RX side

– DPRAM Virtual FIFO overruns

ORSPI4 Scheda tecnica(PDF) 8 Page - Lattice Semiconductor