ORSPI4 datasheet(28/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 10. ORSPI4 Transmit Functional Block Diagram

ORSPI4 Transmit Functional Block Overview

The user can write transmit data and associated control signals to the TX DPRAM bank using either multiple 32- or

64-bit interfaces, or a single aggregated 128-bit interface. The data bus interface is software conﬁgurable. The TX

DPRAM block is made up of 4 conﬁgurable DPRAMs, used for transmit data buffering and clock domain crossing.

The DPRAMs can be conﬁgured via software to support up to 8 virtual partitions each, providing a maximum of 32

virtual FIFOs, each being 256 Bytes deep. Data is read from the DPRAMs according to the conﬁgured Transmit

Calendar within the TX Calendar Control Logic. The control logic provides both the virtual partition address and

BURST_VAL to the Address Map & Arbiter (AMA) block. The AMA services the requested partition and can option-

ally provide idle data if the partition is empty when serviced. The TDP block accepts transmit data and control sig-

nals from the AMA and formats the data according to the SPI4 transmit data protocol. The transmit data is then

serialized within the TDO block. Data is transmitted across the SPI4 interface on a 16-bit LVDS pair bus (TDAT)

which is source synchronous to the LVDS pair clock (TDCLK). The LVDS control signal pair (TCTL) is used to iden-

tify when the content of the SPI4 bus is control versus user data. The interface is an OIF-SPI-4 02.0 compliant

interface that supports data rates in the range of 622-900 Mbps. Additionally, lower speed data in the range of 100-

200 Mbps is also supported. To accommodate dynamic timing the TDP will insert training patterns as conﬁgured.

[A,B]TSTAT

[A,B]TSCLK

DPRAM

SPI[A,B]_k_DATA_j, BEj

SPI[A,B]_k_SOPj, ERRj

SPI[A,B]_k_PORT_j

SPI[A,B]_k_WD_CNT_RST_j

SPI[A,B]_k_WE_j

TDO

[A,B]TDAT

[A,B]TCTL

[A,B]TDCLK

TX Calendar

TSP

TSI

SPI[A,B]_k_PORT_ID

SPI[A,B]_k_STAT

SPI[A,B]_k_BURST_VAL

TLSTAT

TLCLK

TDP

Address

Map &

Arbiter

TDP

k = TX32, TX64 or TX128

SPI[A,B]_k_LINK_DIS_j

SPI[A,B]_k_FIFO_FULL_j

SPI[A,B]_k_CLK_j

SPI[A,B]_k_PORT_ID

Control Logic

PORT_ID

PORT_STAT

AMA_ID

BURST_VAL

SPI[A,B]_k_ADDRj

j = 0, 1, 2 or 3

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