ORSPI4 datasheet(18/263 Pages) LATTICE

18 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge

of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-Chip integration with

true plug-and-play design implementation.

The architecture consists of the following basic elements: Programmable Logic Cells (PLCs), Programmable I/O

cells (PIOs), Embedded Block RAMs (EBRs), plus supporting system-level features. These elements are intercon-

nected with a rich routing fabric of both global and local wires. An array of PLCs is surrounded by common inter-

face blocks that provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around

these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic

core.

Each PLC contains a Programmable Function Unit (PFU), Supplemental Logic Interconnect Cell (SLIC), local rout-

ing resources, and conﬁguration RAM. Most of the FPGA logic is performed in the PFU, but decoders,

PAL-like

functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can

be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions,

and other functions on two output signals.

Large blocks of 512 x 18 quad-port RAM complement the existing distributed PFU memory. The RAM blocks can

be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the

MPI, PLLs, and the Embedded System Bus (ESB).

ORSPI4 Scheda tecnica(PDF) 18 Page - Lattice Semiconductor