ORSPI4 datasheet(12/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

The FIFO Status Update logic block reads the Port and Status information and uses this information to update Port

Descriptor Memory STAT ﬁeld. Whenever a valid STAT ﬁeld has been updated, the associated U-bit ﬁeld is set as

discussed previously. This indicates that the STAT ﬁeld is new and that the Credit ﬁeld for that must be re-evaluated

the next time it is selected as a source for transmit data.

SPI4 Receive Path Overview

In the receive direction, data is received in SPI4 format on the LVDS I/Os at the receive interface. The data is writ-

ten into DPRAM as received and read from the DPRAMs as requested by the FPGA logic. Control information is

also interpreted and buffered and idles and training sequences are removed from the incoming data stream.

Receive FIFO status is transmitted from the Receive Status interface according to a pre-conﬁgured polling

sequence contained within the Receive Calendar. Data is formatted into the SPI4 Receive Status format and sent

to the physical links as either LVDS or LVTTL signals.

The SPI4 block contains the high-speed receive logic. Incoming LVDS signals, in SPI4 format, include the 16-bit

data bus (RDAT[15:0]), a control bit (RCTL) and a source synchronous DDR clock (RDCLK). The incoming data is

deserialized to a 128-bit format and the control information is converted to an 8-bit format.

The SPI4 receive block also detects training patterns and performs dynamic alignment of the incoming data. At

speeds above 700 Mbit/s (350 MHz) it becomes necessary to use dynamic alignment. Skews of up to ± one clock

period can be compensated by the dynamic alignment logic. For low speed incoming data, static alignment can be

chosen through a programmable control bit. Various timing options of receive data vs. receive clock are also pro-

grammable.

The SPI4 block is responsible for decoding the in-band control information. It then forwards both the data and con-

trol information, such as link address, SOP, EOP and error, to the virtual FIFOs. The SPI4 block also parses the

control words embedded within the incoming data. Using this control information, it performs the following func-

tions:

• Checks DIP-4 parity

• Monitors for continuous alignment (if more than a programmable number of DIP-4 parity errors exist, there may

be an alignment problem).

• Removes idle/training words.

• Extracts link address and SOP, EOP and valid packet (no error) signals.

In the receive direction there are also four Dual Port Memory (DPRAM) banks that contain a total of 8K bytes avail-

able for clock domain crossing and/or temporary buffering. As with the transmit buffers, each bank can be further

partitioned up to 8 virtual memories, one for each of 8 ports. The following are the characteristics of the DPRAM

virtual FIFOs:

• The DPRAM memories support asynchronous reads. Each DPRAM bank can be accessed on the FPGA side

with an individual clock.

• For data buffering beyond 32 ports, the DPRAM banks can be used as clock domain crossing FIFOs before writ-

ing the data and control information into an external memory. If fewer ports are supported, the virtual memories

can be aggregated, providing more buffer space for each port.

• Each DPRAM bank has a 32-bit data and 8-bit control read interface to the FPGA. When using the DPRAM

memories, the data can be read as either a 32-, 64-, or 128-bit data bus with associated control signals.

• At any time, the user can poll the status of a FIFO within a DPRAM bank by providing just the read address with-

out a valid read enable.

• A FIFO empty ﬂag is generated by the read control logic to the FPGA. This empty ﬂag can be programmed to

indicate truly empty or < 1/4 full (1/4 full - 1).

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