ORSPI4 datasheet(31/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

SPIA_TX32_ADDR_1[2:0]

FPGA

→ Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum

of eight partitions. More than one port can be conﬁgured to share a virtual

FIFO partition.

SPIA_TX32_DATA_1[31:0]

FPGA

→ Core User Write data. Four writes are required in order to complete an entire

128-bit line. All writes must occur in four write bursts, unless an EOP

occurs.

SPIA_TX32_BE_1[3:0]

FPGA

→ Core Byte enables indicating which bytes within the 32-bit word are valid.

Bit[3]-Byte enable for SPIA_TX32_DATA_0[31:24]

Bit[2]-Byte enable for SPIA_TX32_DATA_0[23:16]

Bit[1]-Byte enable for SPIA_TX32_DATA_0[15:8]

Bit[0]-Byte enable for SPIA_TX32_DATA_0[7:0]

If no BE bits are asserted for a particular location within the DPRAM, port

data will be dropped and no write to the DPRAM will occur.

According to the SPI-4.2 speciﬁcation, the BE bits must be asserted for all

but the last transfer, where an End of Packet or Error may occur. The valid

combinations of BE are as follows:

BE[3:0] = 1111--indicates all four bytes contain valid user data

BE[3:0] = 1110--indicates three bytes are valid. EOP occurs in third Byte.

BE[3:0] = 1100--indicates two bytes are valid. EOP occurs in second Byte.

BE[3:0] = 1000--indicates one byte is valid. EOP occurs in ﬁrst Byte.

SPIA_TX32_SOP_1

FPGA

→ Core Start of Packet indicator. A '1' indicates the start of packet for a particular

port. When operating in either 32- or 64-bit mode, the SOP indicator must

be asserted coincident with the ﬁrst write per address line within the FIFO

partition.

SPIA_TX32_EOP_1

FPGA

→ Core End of Packet indicator. A '1' indicates the end of packet for a particular

port. The EOP may be asserted on any write per address line within the

FIFO partition.

When an EOP is detected by the DPRAM Write Pointer Logic, the address

pointer will be automatically incremented to the next location within the

FIFO partition range.

SPIA_TX32_ERR_1

FPGA

→ Core Packet error indication. A '1' indicates an error has occurred for the current

packet being transmitted. The ERR signal must be asserted coincident with

the EOP signal.

SPIA_TX32_WE_1

FPGA

→ Core Write Enable. A logic '1' causes data on the SPIA_TX32_DATA_1[31:0] bus

to be captured for a write to the DPRAM.

SPIA_TX32_PORT_1[7:0]

FPGA

→ Core SPI4 port indicator, used to associate the current transmit data with a par-

ticular port number.

SPIA_TX32_WD_CNT_RST_

FPGA

→ Core Line Write Termination indicator. This signal causes the FIFO write address

pointer within the embedded core to increment to the next address location

for the addressed partition. This signal can be used for custom applications

as well as for diagnostic test functions.

SPIA_TX32_LINK_DIS_1

FPGA

→ Core Link disable control signal. When asserted to a logic '1', the AMA will cease

polling from a DPRAM. All ports associated with a disabled DPRAM will

remain unserviced until the control signal is deasserted. The AMA will send

IDLE data across the SPI4 link. If the application continues to write data to

that port FIFO, it will eventually ﬁll and provide proper FIFO ﬁll status to the

application.

SPIA_TX32_CLK_1

FPGA

→ Core Transmit write reference clock. The clocks across the different transmit

interfaces are independent from each other, and are not required to be syn-

chronous to each other.

SPIA_TX32_FIFO_FULL_1

Core

→FPGA FIFO full status. The status is given in response to the assertion of any

valid address on the SPIA_TX32_ADDR_1[2:0] bus. This signal will be

asserted to a logic '1' when the current FIFO partition has crossed the con-

ﬁgured ﬁll level within the partition.

Table 2. SPIA Core Transmit FPGA Interface in 32-Bit Mode (Continued)

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

Note: For SPIB replace A with B

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