ORSPI4 datasheet(75/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

SPI4 Receive Logic Blocks - Detailed Description

RDI Block

The SPI4 high-speed Receive Data Input (RDI) block contains the high-speed receive logic for the SPI4 block.

Incoming LVDS signals, in SPI4 format, include the 16-bit data bus (RDAT[15:0]), a control bit (RCTL) and a source

Table 14. SPIA Core Receive FPGA Interface in 128-Bit Mode

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

SPIA_RX128_ADDR[2:0]

FPGA

→ Core FIFO read address.

SPIA_RX128_DATA[127:0]

Core

→FPGA FIFO read data.

SPIA_RX128_BE[15:0]

Core

→FPGA Byte enables

Bit 15- Byte enable for SPIA_RX128_DATA[127:120]

Bit 14- Byte enable for SPIA_RX128_DATA[119:112]

Bit 13- Byte enable for SPIA_RX128_DATA[111:104]

Bit 12- Byte enable for SPIA_RX128_DATA[103:96]

Bit 11- Byte enable for SPIA_RX128_DATA[95:88]

Bit 10- Byte enable for SPIA_RX128_DATA[87:80]

Bit 9- Byte enable for SPIA_RX128_DATA[79:72]

Bit 8- Byte enable for SPIA_RX128_DATA[71:64]

Bit 7 - Byte enable for SPIA_RX128_DATA[63:56]

Bit 6 - Byte enable for SPIA_RX128_DATA[55:48]

Bit 5 - Byte enable for SPIA_RX128_DATA[47:40]

Bit 4 - Byte enable for SPIA_RX128_DATA[39:32]

Bit 3 - Byte enable for SPIA_RX128_DATA[31:24]

Bit 2 - Byte enable for SPIA_RX128_DATA[23:16]

Bit 1 - Byte enable for SPIA_RX128_DATA[15:8]

Bit 0 - Byte enable for SPIA_RX128_DATA[7:0]

SPIA_RX128_PORTID[7:0]

Core

→FPGA Port ID for the current data.

SPIA_RX128_SOP

Core

→FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.

SPIA_RX128_EOP

Core

→FPGA End of Packet Indicator. A ‘1’ indicates end of packet.

SPIA_RX128_ERR

Core

→FPGA Error. A ‘1’ indicates an error in the current word.

SPIA_RX128_FIFO_EMPTY

Core

→FPGA FIFO Empty ﬂag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0]

software register bit in address 0x30920. When this bit is set to ‘0’, (default)

the empty ﬂag indicates truly empty.

When this bit is set to ‘1’, the empty ﬂag indicates that the FIFO is 1/4 full -1.

ASTOP_ON_EOP

FPGA

→ Core Timing control for handling end of packet.

SPIA_RX128_CLK

FPGA

→ Core FIFO read clock.

SPIA_RX128_RD

FPGA

→ Core FIFO read enable.

SPIA_RX128_PORT_ID[7:0]

FPGA

→ Core Port ID used by the core as write address into the status RAM.

SPIA_RX128_STAT[1:0]

FPGA

→ Core Port Status corresponding to SPIA_RX128_PORT_ID

SPIA_RX128_EXT_STAT_EN

FPGA

→ Core When set to ‘1’, the status from SPIA_RX128_STAT will be sent on the

SPI4 status i/f.

SPIA_RX128_PSS_WE

FPGA

→ Core Write enable to the internal Status RAM.

SPIA_RX128_PSS_CLK

FPGA

→ Core Write clock to the internal Status RAM.

Misc.

I/Os

SPI_DATM_A

FPGA

→ Core Valid only during static data capture. Should be set to ‘0’ in dynamic align-

ment mode.

‘0’ - Bypass delay line circuit on the clock (ARDCLK) path.

‘1’ - Enables delay line circuit on the ARDCLK path.

SPI_DLYTAP_A[2:0]

FPGA

→ Core These bits control the effective delay of the delay line circuit on the ARD-

CLK path. Valid values are from 0-6.

ARLSCLK_F

Core

→FPGA Internal clock (ARDCLK/4) used to clock all receive status logic.

Note: For SPIB replace A with B

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