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HD6432138SW Scheda tecnica(PDF) 340 Page - Renesas Technology Corp |
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HD6432138SW Scheda tecnica(HTML) 340 Page - Renesas Technology Corp |
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340 / 1061 page ![]() Section 11 16-Bit Free-Running Timer Rev. 4.00 Jun 06, 2006 page 286 of 1004 REJ09B0301-0400 Bit 1 OLVLA Description 0 0 output at compare-match A (Initial value) 1 1 output at compare-match A Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in response to compare-match B (signal indicating a match between the FRC and OCRB values). Bit 0 OLVLB Description 0 0 output at compare-match B (Initial value) 1 1 output at compare-match B 11.2.10 Module Stop Control Register (MSTPCR) 7 MSTP15 0 R/W Bit Initial value Read/Write 6 MSTP14 0 R/W 5 MSTP13 1 R/W 4 MSTP12 1 R/W 3 MSTP11 1 R/W 2 MSTP10 1 R/W 1 MSTP9 1 R/W 0 MSTP8 1 R/W 7 MSTP7 1 R/W 6 MSTP6 1 R/W 5 MSTP5 1 R/W 4 MSTP4 1 R/W 3 MSTP3 1 R/W 2 MSTP2 1 R/W 1 MSTP1 1 R/W 0 MSTP0 1 R/W MSTPCRH MSTPCRL MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and module stop mode is entered. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 5—Module Stop (MSTP13): Specifies the FRT module stop mode. MSTPCRH Bit 5 MSTP13 Description 0 FRT module stop mode is cleared 1 FRT module stop mode is set (Initial value) |
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