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HD6432138SW Scheda tecnica(PDF) 342 Page - Renesas Technology Corp |
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HD6432138SW Scheda tecnica(HTML) 342 Page - Renesas Technology Corp |
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342 / 1061 page ![]() Section 11 16-Bit Free-Running Timer Rev. 4.00 Jun 06, 2006 page 288 of 1004 REJ09B0301-0400 N + 1 N FRC input clock φ FRC External clock input pin Figure 11.4 Increment Timing with External Clock Source 11.3.2 Output Compare Output Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A. N + 1 N N + 1 N N OCRA φ Compare-match A signal FRC OLVLA Output compare A output pin FTOA Clear* Note: * Vertical arrows ( ) indicate instructions executed by software. N Figure 11.5 Timing of Output Compare A Output |
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