H8SSLASH2218 datasheet(643/750 Pages) RENESAS

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Section 19 Clock Pulse Generator

Rev.6.00 Jun. 03, 2008 Page 595 of 698

REJ09B0074-0600

Section 19 Clock Pulse Generator

This LSI has an on-chip clock pulse generator that generates the system clock (

φ), the bus master

clock, and internal clocks. The clock pulse generator consists of a main clock oscillator, duty

adjustment circuit, clock select circuit, medium-speed clock divider, bus master clock selection

circuit, subclock oscillator, waveform shaping circuit, PLL (Phase Locked Loop) circuit, and USB

operating clock selection circuit. A block diagram of clock pulse generator is shown in figure

19.1.

Duty

adjustment

circuit

EXTAL

XTAL

Main

clock

oscillator

USB

operation

clock

selection circuit

OSC1

OSC2

Subclock

oscillator

Waveform

generation

circuit

Medium-

speed

clock divider

System clock

φ pin

USB operation

clock

to USB

RTC clock

to RTC

Internal clock

to peripheral

modules

Bus master clock

to CPU,

DMAC

USB clock

to USB

φ/2

φ/32

SCK2 to SCK0

UCKS3 to UCKS0

SCKCR

RFCUT

48MHz

LPWRCR

UCTLR

Bus

master

clock

selection

circuit

Clock

selection

circuit

φ SUB

Legend:

LPWRCR: Low power control register

SCKCR:

System clock control register

UCTLR:

USB control register

PLL

circuit

Figure 19.1 Block Diagram of Clock Pulse Generator

The frequency of the main clock oscillator can be changed by software by means of settings in the

low-power control register (LPWRCR) and system clock control register (SCKCR). PLL 48-MHz

clock can be selected by software by means of setting the USB control register (UCTLR). For

details, refer to section 14, Universal Serial Bus (USB).

CPG0600B_000020020900

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