H8SSLASH2218 datasheet(645/750 Pages) RENESAS

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Section 19 Clock Pulse Generator

Rev.6.00 Jun. 03, 2008 Page 597 of 698

REJ09B0074-0600

Bit

Bit Name Initial Value R/W

Description

SCK2

SCK1

SCK0

R/W

System Clock Select 2 to 0

These bits select the bus master clock. To operate in

subactive mode or watch mode, clear the SCK2 to SCK0

bits to 0.

000: High-speed mode

001: Medium-speed clock is

φ/2

010: Medium-speed clock is

φ/4

011: Medium-speed clock is

φ/8

100: Medium-speed clock is

φ/16

101: Medium-speed clock is

φ/32

×: Setting prohibited

Legend:

×: Don’t care

19.1.2

Low Power Control Register (LPWRCR)

LPWRCR performs power-down mode control, selects sampling frequency for eliminating noise,

performs subclock oscillator control, and selects whether or not built-in feedback resistance and

duty adjustment circuit of the system clock generator used.

Bit

Bit Name Initial Value R/W

Description

DTON

R/W

Direct Transition ON Flag

0: When the SLEEP instruction is executed in high-speed

mode or medium-speed mode, operation shifts to sleep

mode, software standby mode, or watch mode*.

When the SLEEP instruction is executed in subactive

mode, operation shifts to subsleep mode or watch mode.

1: When the SLEEP instruction is executed in high-speed

mode or medium-speed mode, operation shifts directly to

subactive mode, or shifts to sleep mode or software

standby mode.

When the SLEEP instruction is executed in subactive

mode, operation shifts directly to high-speed mode, or

shifts to subsleep mode.

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