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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2218 Scheda tecnica(PDF) 644 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 644 Page - Renesas Technology Corp |
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644 / 750 page  Section 19 Clock Pulse Generator Rev.6.00 Jun. 03, 2008 Page 596 of 698 REJ09B0074-0600 19.1 Register Descriptions The on-chip clock pulse generator has the following registers. • System clock control register (SCKCR) • Low-power control register (LPWRCR) 19.1.1 System Clock Control Register (SCKCR) SCKCR controls φ clock output and medium-speed mode. Bit Bit Name Initial Value R/W Description 7 PSTOP 0 R/W φ Clock Output Disable Controls φ output. The operation of this bit changes depending on the operating mode. For details, see section 20.11, φ Clock Output Disabling Function. 0: φ output, fixed high, or high impedance 1: Fixed high or high impedance 6 — 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. 5, 4 — All 0 — Reserved These bits are always read as 0. 3 — 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. |
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