ATtiny261-ESSZ datasheet(65/227 Pages) ATMEL

65 / 227 page

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

• Port B, Bit 0 - MOSI/ DI/ SDA/ OC1A/ PCINT8

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB0. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit.

DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port

functions, so pin must be configure as an input for DI function.

SDA: Two-wire mode Serial Interface Data.

OC1A: Inverted Output Compare Match output: The PB0 pin can serve as an external output for

the Timer/Counter1 Compare Match B when configured as an output (DDB0 set). The OC1A pin

is also the inverted output pin for the PWM mode timer function.

PCINT8: Pin Change Interrupt source 8.

Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 12-5 on page 61.

Note:

1. 1 when the Fuse is “0” (Programmed).

Table 12-4.

Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name

PB7/RESET/dW/

ADC10/PCINT15

PB6/ADC9/T0/INT0/

PCINT14

PB5/XTAL2/CLKO/

OC1D/ADC8/PCINT13(1)

PB4/XTAL1/OC1D/

ADC7/PCINT12(1)

PUOE

RSTDISBL(1) •

DWEN(1)

INTRC • EXTCLK

INTRC

PUOV

DDOE

RSTDISBL(1) •

DWEN(1)

INTRC • EXTCLK

INTRC

DDOV

debugWire Transmit 0

PVOE

OC1D Enable

PVOV

OC1D

PTOE

DIEOE

RSTDISBL + (PCINT5

• PCIE + ADC9D)

INTRC • EXTCLK + PCINT4 •

PCIE + ADC8D

INTRC + PCINT12

• PCIE + ADC7D

DIEOV

ADC10D

ADC9D

(INTRC • EXTCLK) + ADC8D INTRC • ADC7D

PCINT15

T0/INT0/PCINT14

PCINT13

PCINT12

AIO

RESET / ADC10

ADC9

XTAL2, ADC8

XTAL1, ADC7

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