ATtiny261-ESSZ datasheet(18/227 Pages) ATMEL

18 / 227 page

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-

nal data SRAM in the ATtiny261/461/861 are all accessible through all these addressing modes.

The Register File is described in “General Purpose Register File” on page 12.

Figure 6-2.

Data Memory Map

6.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 6-3.

Figure 6-3.

On-chip Data SRAM Access Cycles

6.3

EEPROM Data Memory

The ATtiny261/461/861 contains 128/256/512 bytes of data EEPROM memory. It is organized

as a separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register. For a detailed description of Serial data

downloading to the EEPROM, see page 183.

32 Registers

64 I/O Registers

Internal SRAM

(128/256/512 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0DF/0x15F/0x25F

0x0060

Data Memory

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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